linux.git/drivers/soc/imx, branch v5.15

Revert "soc: imx8m: change to use platform driver"

2021-07-15T11:02:44+00:00

With the SoC matching changed to a platform driver the match data
is available only after other drivers, which may rely on it are
already probed. This breaks at least the CAAM driver on i.MX8M.
Revert the change until all those drivers have been audited and
changed to be able to eal with match data being available later
in the boot process.

Fixes: 7d981405d0fd ("soc: imx8m: change to use platform driver")
Signed-off-by: Lucas Stach 
Tested-by: Frieder Schrempf 
Acked-by: Peng Fan 
Signed-off-by: Shawn Guo

Merge tag 'arm-drivers-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2021-07-10T16:46:20+00:00

Pull ARM driver updates from Olof Johansson:

 - Reset controllers: Adding support for Microchip Sparx5 Switch.

 - Memory controllers: ARM Primecell PL35x SMC memory controller driver
   cleanups and improvements.

 - i.MX SoC drivers: Power domain support for i.MX8MM and i.MX8MN.

 - Rockchip: RK3568 power domains support + DT binding updates,
   cleanups.

 - Qualcomm SoC drivers: Amend socinfo with more SoC/PMIC details,
   including support for MSM8226, MDM9607, SM6125 and SC8180X.

 - ARM FFA driver: "Firmware Framework for ARMv8-A", defining management
   interfaces and communication (including bus model) between partitions
   both in Normal and Secure Worlds.

 - Tegra Memory controller changes, including major rework to deal with
   identity mappings at boot and integration with ARM SMMU pieces.

* tag 'arm-drivers-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (120 commits)
  firmware: turris-mox-rwtm: add marvell,armada-3700-rwtm-firmware compatible string
  firmware: turris-mox-rwtm: show message about HWRNG registration
  firmware: turris-mox-rwtm: fail probing when firmware does not support hwrng
  firmware: turris-mox-rwtm: report failures better
  firmware: turris-mox-rwtm: fix reply status decoding function
  soc: imx: gpcv2: add support for i.MX8MN power domains
  dt-bindings: add defines for i.MX8MN power domains
  firmware: tegra: bpmp: Fix Tegra234-only builds
  iommu/arm-smmu: Use Tegra implementation on Tegra186
  iommu/arm-smmu: tegra: Implement SID override programming
  iommu/arm-smmu: tegra: Detect number of instances at runtime
  dt-bindings: arm-smmu: Add Tegra186 compatible string
  firmware: qcom_scm: Add MDM9607 compatible
  soc: qcom: rpmpd: Add MDM9607 RPM Power Domains
  soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's
  soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's
  dt-bindings: soc: rockchip: drop unnecessary #phy-cells from grf.yaml
  memory: emif: remove unused frequency and voltage notifiers
  memory: fsl_ifc: fix leak of private memory on probe failure
  memory: fsl_ifc: fix leak of IO mapping on probe failure
  ...

soc: imx: gpcv2: add support for i.MX8MN power domains

2021-06-12T03:51:28+00:00

This adds support for the power domains founds on i.MX8MN. The Nano
has fewer domains than the Mini, and the access to some of these domains
is different than that of the Mini, the Mini power domains cannot be
reused.

Signed-off-by: Adam Ford 
Acked-by: Krzysztof Kozlowski 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: move reset assert after requesting domain power up

2021-05-27T01:01:36+00:00

The i.MX8MM VPU power up sequence is a bit special, it must follow:
1. request power up
2. reset assert
3. reset deassert

This change in this patch will not affect other domains, because
the power domain default is in asserted state, unless bootloader
deassert the reset. It also applies to GPU power domain.

Reviewed-by: Frieder Schrempf 
Tested-by: Frieder Schrempf 
Signed-off-by: Peng Fan 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: Add support for missing i.MX8MM VPU/DISPMIX power domains

2021-05-27T01:01:36+00:00

With the BLK-CTL driver now in place, let's add the missing domains.

Tested-by: Frieder Schrempf 
Signed-off-by: Lucas Stach 
Signed-off-by: Frieder Schrempf 
Signed-off-by: Peng Fan 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: add support for i.MX8MM power domains

2021-05-27T01:01:36+00:00

This adds support for the power domains found on i.MX8MM. The 2D and 3D
GPU domains are abstracted as a single domain in the driver, as they can't
be powered up/down individually due to a shared reset.

Tested-by: Frieder Schrempf 
Reviewed-by: Frieder Schrempf 
Signed-off-by: Lucas Stach 
Signed-off-by: Peng Fan 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: add support for optional resets

2021-05-23T02:58:12+00:00

Normally the reset for the devices inside the power domain is
triggered automatically from the PGC in the power-up sequencing,
however on i.MX8MM this doesn't work for the GPU power domains.

Add support for triggering the reset explicitly during the power
up sequencing.

Tested-by: Frieder Schrempf 
Reviewed-by: Frieder Schrempf 
Signed-off-by: Lucas Stach 
Signed-off-by: Peng Fan 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: allow domains without power-sequence control

2021-05-23T02:58:10+00:00

Some of the PGC domains only control the handshake with the ADB400
and don't have any power sequence controls. Make such domains work
by allowing the pxx and map bits to be empty and skip all actions
using those controls.

Tested-by: Frieder Schrempf 
Reviewed-by: Frieder Schrempf 
Signed-off-by: Lucas Stach 
Signed-off-by: Peng Fan 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: add runtime PM support for power-domains

2021-05-23T02:58:07+00:00

This allows to nest domains into other power domains and have the
parent domain powered up/down as required by the child domains.

Tested-by: Frieder Schrempf 
Reviewed-by: Frieder Schrempf 
Signed-off-by: Lucas Stach 
Signed-off-by: Peng Fan 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: wait for ADB400 handshake

2021-05-23T02:58:04+00:00

New reference manuals show that there is actually a status bit for
the ADB400 handshake. Add a poll loop to wait for the ADB400 to
acknowledge our request.

[Peng Fan: i.MX8MM has blk ctl module, the handshake can only finish
 after setting blk ctl. The blk ctl driver will set the bus clk bit and
 the handshake will finish there. we just add a delay and suppose the
 handshake will finish after that.]

Tested-by: Frieder Schrempf 
Signed-off-by: Lucas Stach 
Signed-off-by: Peng Fan 
Signed-off-by: Shawn Guo