linux.git/drivers/soc/bcm, branch v5.10

soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines

2020-09-06T19:43:02+00:00

Change the RACPREFDATA(x) setting to prefetch the next 256-byte line
after 4 consecutive lines have been used, instead of after 2 consecutive
lines. This does improve the synthetic memcpy benchmark by an additional
+0.5% on top of the previous change for Cortex-A72 CPUs.

Signed-off-by: Florian Fainelli

soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2

2020-09-04T20:48:49+00:00

Change the RAC prefetch distance from +/- 1 to +/- 2 for Cortex-A72 CPUs
since this provides an average of a 3.8% performance increase for
synthetic memcpy benchmarks.

Signed-off-by: Florian Fainelli

soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165

2020-09-04T20:48:42+00:00

72165 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it
according to the existing values we have.

Signed-off-by: Florian Fainelli

soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164

2020-09-04T20:44:32+00:00

72164 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it
according to the existing values we have.

Signed-off-by: Florian Fainelli

soc: bcm: add BCM63xx power domain driver

2020-08-17T16:14:04+00:00

BCM6318, BCM6328, BCM6362 and BCM63268 SoCs have a power domain controller
to enable/disable certain components in order to save power.

Signed-off-by: Álvaro Fernández Rojas 
Reviewed-by: Florian Fainelli 
Signed-off-by: Florian Fainelli

soc: bcm: brcmstb: biuctrl: Enable Read-ahead cache

2020-08-17T16:14:04+00:00

Brahma-B53 and Cortex-A72 CPUs integrated on Broadcom STB SoCs feature a
read-ahead cache that performs cache line size adaptation between the
bus interface unit and the memory controller.

On 32-bit ARM kernels we have to resort to a full featured read-ahead
cache driver under arch/arm/mm/cache-b15-rac.c (CONFIG_CACHE_B15_RAC)
because there are still cache maintenance operations by set/ways/index
that cannot be transparently handled by the ARM Coherency Extension that
the read-ahead cache interfaces to.

The 64-bit ARM kernel however has long deprecated all of those, so this
is simply a one time configuration.

Signed-off-by: Florian Fainelli

soc: bcm: brcmstb: biuctrl: Update programming for 7211

2020-01-05T21:44:04+00:00

Add a matching entry for 7211 which can be programmed with the same
BIUCTRL settings as other Brahma-B53 based SoCs. While at it, rename the
function to include a72 in the name to reflect this applies to both
types of 64-bit capable CPUs that we support (Brahma-B53 and
Cortex-A72).

Signed-off-by: Florian Fainelli

soc: bcm: brcmstb: biuctrl: Update layout for A72 on 7211

2020-01-05T21:44:04+00:00

The BIUCTRL layout is a little different on 7211 which is equipped with
a Cortex-A72, account for those register offset differences. We will
match 7211 specifically in a subsequent commit.

Signed-off-by: Florian Fainelli

soc: bcm: brcmstb: biuctrl: Tune interface for 7255 and 7216

2020-01-05T21:44:04+00:00

7255 and 7216 are some of the latest chips that were produced and
support the full register range configuration for the BIU, add the two
entries to get the expected programming.

Signed-off-by: Florian Fainelli

soc: bcm: brcmstb: biuctrl: Tune 7260 BIU interface

2020-01-05T21:44:04+00:00

7260A0 and B0 are both supported, and 7260A0 has a small difference in
that it does not support the write-back control register, which is why
we have a different array of registers. Update the comment above
b53_cpubiuctrl_no_wb_regs to denote that difference.

Signed-off-by: Florian Fainelli