linux.git/drivers/reset/Kconfig, branch v6.16 Linux kernel source tree reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P) 2025-05-05T13:18:35+00:00 Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2025-04-15T19:51:30+00:00 e3911d7f865bbc704205f45333e491e4034942c7 Implement a USB2PHY port reset driver for the Renesas RZ/V2H(P) SoC. Enable control of USB2.0 PHY reset and power-down operations, including assert and deassert functionalities for the PHY. Leverage device tree (OF) data to support future SoCs with similar USB2PHY hardware but varying register configurations. Define initialization values and control register settings to ensure flexibility for upcoming platforms. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/20250415195131.281060-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
Implement a USB2PHY port reset driver for the Renesas RZ/V2H(P) SoC.
Enable control of USB2.0 PHY reset and power-down operations, including
assert and deassert functionalities for the PHY.

Leverage device tree (OF) data to support future SoCs with similar USB2PHY
hardware but varying register configurations. Define initialization values
and control register settings to ensure flexibility for upcoming platforms.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20250415195131.281060-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
reset: thead: Add TH1520 reset controller driver 2025-04-07T08:19:27+00:00 Michal Wilczynski m.wilczynski@samsung.com 2025-03-03T15:25:11+00:00 4a65326311aba694faafcef9e3c0ef7ae1b722e6 Add reset controller driver for the T-HEAD TH1520 SoC that manages hardware reset lines for various subsystems. The driver currently implements support for GPU reset control, with infrastructure in place to extend support for NPU and Watchdog Timer resets in future updates. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Link: https://lore.kernel.org/r/20250303152511.494405-3-m.wilczynski@samsung.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
Add reset controller driver for the T-HEAD TH1520 SoC that manages
hardware reset lines for various subsystems. The driver currently
implements support for GPU reset control, with infrastructure in place
to extend support for NPU and Watchdog Timer resets in future updates.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Link: https://lore.kernel.org/r/20250303152511.494405-3-m.wilczynski@samsung.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
reset: imx: Add SCU reset driver for i.MX8QXP and i.MX8QM 2025-03-13T08:06:27+00:00 Frank Li Frank.Li@nxp.com 2025-02-10T20:59:21+00:00 6b64fde5c183b5ef5b0f0f7321408caf3b876187 Add System Controller Firmware(SCU) reset driver for i.MX8QM and i.MX8QXP. SCU Manage resets for peripherals such as MIPI CSI. Currently, support two reset sources: IMX_SC_R_CSI_0 and IMX_SC_R_CSI_1. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250210-8qxp_camera-v3-2-324f5105accc@nxp.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
Add System Controller Firmware(SCU) reset driver for i.MX8QM and i.MX8QXP.
SCU Manage resets for peripherals such as MIPI CSI. Currently, support two
reset sources: IMX_SC_R_CSI_0 and IMX_SC_R_CSI_1.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250210-8qxp_camera-v3-2-324f5105accc@nxp.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 2024-11-23T01:02:25+00:00 Linus Torvalds torvalds@linux-foundation.org 2024-11-23T01:02:25+00:00 9f3a2ba62c7226a6604b8aaeb92b5ff906fa4e6b Pull clk updates from Stephen Boyd: "The core framework gained a clk provider helper, a clk consumer helper, and some unit tests for the assigned clk rates feature in DeviceTree. On the vendor driver side, we gained a whole pile of SoC driver support detailed below. The majority in the diffstat is Qualcomm, but there's also quite a few Samsung and Mediatek clk driver additions in here as well. The top vendors is quite common, but the sheer amount of new drivers is uncommon, so I'm anticipating a larger number of fixes for clk drivers this cycle. Core: - devm_clk_bulk_get_all_enabled() to return number of clks acquired - devm_clk_hw_register_gate_parent_hw() helper to modernize drivers - KUnit tests for clk-assigned-rates{,-u64} New Drivers: - Marvell PXA1908 SoC clks - Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver - TWL6030 clk driver - Nuvoton Arbel BMC NPCM8XX SoC clks - MediaTek MT6735 SoC clks - MediaTek MT7620, MT7628 and MT7688 MMC clks - Add a driver for gated fixed rate clocks - Global clock controllers for Qualcomm QCS8300 and IPQ5424 SoCs - Camera, display and video clock controllers for Qualcomm SA8775P SoCs - Global, display, GPU, TCSR, and RPMh clock controllers for Qualcomm SAR2130P - Global, camera, display, GPU, and video clock controllers for Qualcomm SM8475 SoCs - RTC power domain and Battery Backup Function (VBATTB) clock support for the Renesas RZ/G3S SoC - Qualcomm IPQ9574 alpha PLLs - Support for i.MX91 CCM in the i.MX93 driver - Microchip LAN969X SoC clks - Cortex-A55 core clocks and Interrupt Control Unit (ICU) clock and reset on Renesas RZ/V2H(P) - Samsung ExynosAutov920 clk drivers for PERIC1, MISC, HSI0 and HSI1 - Samsung Exynos8895 clk drivers for FSYS0/1, PERIC0/1, PERIS and TOP Updates: - Convert more clk bindings to YAML - Various clk driver cleanups: NULL checks, add const, etc. - Remove END/NUM #defines that count number of clks in various binding headers - Continue moving reset drivers to drivers/reset via auxiliary bus" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (162 commits) clk: clk-loongson2: Fix potential buffer overflow in flexible-array member access clk: Fix invalid execution of clk_set_rate clk: clk-loongson2: Fix memory corruption bug in struct loongson2_clk_provider clk: lan966x: make it selectable for ARCH_LAN969X clk: eyeq: add EyeQ6H west fixed factor clocks clk: eyeq: add EyeQ6H central fixed factor clocks clk: eyeq: add EyeQ5 fixed factor clocks clk: eyeq: add fixed factor clocks infrastructure clk: eyeq: require clock index with phandle in all cases clk: fixed-factor: add clk_hw_register_fixed_factor_index() function dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles clk: clk-axi-clkgen: make sure to enable the AXI bus clock dt-bindings: clock: axi-clkgen: include AXI clk clk: mmp: Add Marvell PXA1908 MPMU driver clk: mmp: Add Marvell PXA1908 APMU driver clk: mmp: Add Marvell PXA1908 APBCP driver clk: mmp: Add Marvell PXA1908 APBC driver dt-bindings: clock: Add Marvell PXA1908 clock bindings clk: mmp: Switch to use struct u32_fract instead of custom one ... 
Pull clk updates from Stephen Boyd:
 "The core framework gained a clk provider helper, a clk consumer
  helper, and some unit tests for the assigned clk rates feature in
  DeviceTree. On the vendor driver side, we gained a whole pile of SoC
  driver support detailed below. The majority in the diffstat is
  Qualcomm, but there's also quite a few Samsung and Mediatek clk driver
  additions in here as well. The top vendors is quite common, but the
  sheer amount of new drivers is uncommon, so I'm anticipating a larger
  number of fixes for clk drivers this cycle.

  Core:
   - devm_clk_bulk_get_all_enabled() to return number of clks acquired
   - devm_clk_hw_register_gate_parent_hw() helper to modernize drivers
   - KUnit tests for clk-assigned-rates{,-u64}

  New Drivers:
   - Marvell PXA1908 SoC clks
   - Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver
   - TWL6030 clk driver
   - Nuvoton Arbel BMC NPCM8XX SoC clks
   - MediaTek MT6735 SoC clks
   - MediaTek MT7620, MT7628 and MT7688 MMC clks
   - Add a driver for gated fixed rate clocks
   - Global clock controllers for Qualcomm QCS8300 and IPQ5424 SoCs
   - Camera, display and video clock controllers for Qualcomm SA8775P
     SoCs
   - Global, display, GPU, TCSR, and RPMh clock controllers for Qualcomm
     SAR2130P
   - Global, camera, display, GPU, and video clock controllers for
     Qualcomm SM8475 SoCs
   - RTC power domain and Battery Backup Function (VBATTB) clock support
     for the Renesas RZ/G3S SoC
   - Qualcomm IPQ9574 alpha PLLs
   - Support for i.MX91 CCM in the i.MX93 driver
   - Microchip LAN969X SoC clks
   - Cortex-A55 core clocks and Interrupt Control Unit (ICU) clock and
     reset on Renesas RZ/V2H(P)
   - Samsung ExynosAutov920 clk drivers for PERIC1, MISC, HSI0 and HSI1
   - Samsung Exynos8895 clk drivers for FSYS0/1, PERIC0/1, PERIS and TOP

  Updates:
   - Convert more clk bindings to YAML
   - Various clk driver cleanups: NULL checks, add const, etc.
   - Remove END/NUM #defines that count number of clks in various
     binding headers
   - Continue moving reset drivers to drivers/reset via auxiliary bus"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (162 commits)
  clk: clk-loongson2: Fix potential buffer overflow in flexible-array member access
  clk: Fix invalid execution of clk_set_rate
  clk: clk-loongson2: Fix memory corruption bug in struct loongson2_clk_provider
  clk: lan966x: make it selectable for ARCH_LAN969X
  clk: eyeq: add EyeQ6H west fixed factor clocks
  clk: eyeq: add EyeQ6H central fixed factor clocks
  clk: eyeq: add EyeQ5 fixed factor clocks
  clk: eyeq: add fixed factor clocks infrastructure
  clk: eyeq: require clock index with phandle in all cases
  clk: fixed-factor: add clk_hw_register_fixed_factor_index() function
  dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks
  dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles
  clk: clk-axi-clkgen: make sure to enable the AXI bus clock
  dt-bindings: clock: axi-clkgen: include AXI clk
  clk: mmp: Add Marvell PXA1908 MPMU driver
  clk: mmp: Add Marvell PXA1908 APMU driver
  clk: mmp: Add Marvell PXA1908 APBCP driver
  clk: mmp: Add Marvell PXA1908 APBC driver
  dt-bindings: clock: Add Marvell PXA1908 clock bindings
  clk: mmp: Switch to use struct u32_fract instead of custom one
  ...
Merge branches 'clk-samsung', 'clk-microchip', 'clk-imx', 'clk-amlogic' and 'clk-allwinner' into clk-next 2024-11-19T04:01:28+00:00 Stephen Boyd sboyd@kernel.org 2024-11-19T04:01:28+00:00 0cf32b1f37180bba9b7d2c54e902eadc44a4f7a7 * clk-samsung: clk: samsung: Introduce Exynos8895 clock driver clk: samsung: clk-pll: Add support for pll_{1051x,1052x} dt-bindings: clock: samsung: Add Exynos8895 SoC clk: samsung: gs101: make all ufs related clocks critical clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions clk: samsung: Fix out-of-bound access of of_match_node() dt-bindings: clock: samsung: remove define with number of clocks for FSD clk: samsung: fsd: do not define number of clocks in bindings clk: samsung: Fix errors reported by checkpatch clk: samsung: Fix block comment style warnings reported by checkpatch * clk-microchip: clk: lan966x: add support for lan969x SoC clock driver clk: lan966x: prepare driver for lan969x support clk: lan966x: make clk_names const char * const dt-bindings: clock: add support for lan969x * clk-imx: clk: imx: imx8-acm: Fix return value check in clk_imx_acm_attach_pm_domains() clk: imx: lpcg-scu: Skip HDMI LPCG clock save/restore clk: imx: clk-scu: fix clk enable state save and restore clk: imx: fracn-gppll: fix pll power up clk: imx: fracn-gppll: correct PLL initialization flow clk: imx: lpcg-scu: SW workaround for errata (e10858) clk: imx: add i.MX91 clk dt-bindings: clock: Add i.MX91 clock support dt-bindings: clock: imx93: Drop IMX93_CLK_END macro definition clk: imx93: Move IMX93_CLK_END macro to clk driver clk: imx95-blk-ctl: Add one clock gate for HSIO block dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL * clk-amlogic: clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX clk: amlogic: axg-audio: use the auxiliary reset driver reset: amlogic: Fix small whitespace issue reset: amlogic: add auxiliary reset driver support reset: amlogic: split the device core and platform probe reset: amlogic: move drivers to a dedicated directory reset: amlogic: add reset status support reset: amlogic: use reset number instead of register count reset: amlogic: add driver parameters reset: amlogic: make parameters unsigned reset: amlogic: use generic data matching function reset: amlogic: convert driver to regmap dt-bindings: clock: convert amlogic,meson8b-clkc.txt to dtschema clk: meson: meson8b: remove spinlock clk: meson: mpll: Delete a useless spinlock from the MPLL clk: meson: s4: pll: fix frac maximum value for hifi_pll clk: meson: c3: pll: fix frac maximum value for hifi_pll clk: meson: Support PLL with fixed fractional denominators clk: meson: s4: pll: hifi_pll support fractional multiplier * clk-allwinner: clk: sunxi-ng: Use of_property_present() for non-boolean properties clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset clk: sunxi-ng: Constify struct ccu_reset_map clk: sunxi-ng: h616: Add sigma-delta modulation settings for audio PLL 
* clk-samsung:
  clk: samsung: Introduce Exynos8895 clock driver
  clk: samsung: clk-pll: Add support for pll_{1051x,1052x}
  dt-bindings: clock: samsung: Add Exynos8895 SoC
  clk: samsung: gs101: make all ufs related clocks critical
  clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support
  dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions
  clk: samsung: Fix out-of-bound access of of_match_node()
  dt-bindings: clock: samsung: remove define with number of clocks for FSD
  clk: samsung: fsd: do not define number of clocks in bindings
  clk: samsung: Fix errors reported by checkpatch
  clk: samsung: Fix block comment style warnings reported by checkpatch

* clk-microchip:
  clk: lan966x: add support for lan969x SoC clock driver
  clk: lan966x: prepare driver for lan969x support
  clk: lan966x: make clk_names const char * const
  dt-bindings: clock: add support for lan969x

* clk-imx:
  clk: imx: imx8-acm: Fix return value check in clk_imx_acm_attach_pm_domains()
  clk: imx: lpcg-scu: Skip HDMI LPCG clock save/restore
  clk: imx: clk-scu: fix clk enable state save and restore
  clk: imx: fracn-gppll: fix pll power up
  clk: imx: fracn-gppll: correct PLL initialization flow
  clk: imx: lpcg-scu: SW workaround for errata (e10858)
  clk: imx: add i.MX91 clk
  dt-bindings: clock: Add i.MX91 clock support
  dt-bindings: clock: imx93: Drop IMX93_CLK_END macro definition
  clk: imx93: Move IMX93_CLK_END macro to clk driver
  clk: imx95-blk-ctl: Add one clock gate for HSIO block
  dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL

* clk-amlogic:
  clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX
  clk: amlogic: axg-audio: use the auxiliary reset driver
  reset: amlogic: Fix small whitespace issue
  reset: amlogic: add auxiliary reset driver support
  reset: amlogic: split the device core and platform probe
  reset: amlogic: move drivers to a dedicated directory
  reset: amlogic: add reset status support
  reset: amlogic: use reset number instead of register count
  reset: amlogic: add driver parameters
  reset: amlogic: make parameters unsigned
  reset: amlogic: use generic data matching function
  reset: amlogic: convert driver to regmap
  dt-bindings: clock: convert amlogic,meson8b-clkc.txt to dtschema
  clk: meson: meson8b: remove spinlock
  clk: meson: mpll: Delete a useless spinlock from the MPLL
  clk: meson: s4: pll: fix frac maximum value for hifi_pll
  clk: meson: c3: pll: fix frac maximum value for hifi_pll
  clk: meson: Support PLL with fixed fractional denominators
  clk: meson: s4: pll: hifi_pll support fractional multiplier

* clk-allwinner:
  clk: sunxi-ng: Use of_property_present() for non-boolean properties
  clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset
  clk: sunxi-ng: Constify struct ccu_reset_map
  clk: sunxi-ng: h616: Add sigma-delta modulation settings for audio PLL
reset: mchp: sparx5: Allow building as a module 2024-10-24T10:09:34+00:00 Clément Léger clement.leger@bootlin.com 2024-10-14T12:46:34+00:00 996737ef676f5fea11a5e0a79a6e03ff13204490 This reset controller can be used by the LAN966x PCI device. The LAN966x PCI device driver can be built as a module and this reset controller driver has no reason to be a builtin driver in that case. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20241014124636.24221-6-herve.codina@bootlin.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
This reset controller can be used by the LAN966x PCI device.

The LAN966x PCI device driver can be built as a module and this reset
controller driver has no reason to be a builtin driver in that case.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20241014124636.24221-6-herve.codina@bootlin.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
reset: mchp: sparx5: Add MCHP_LAN966X_PCI dependency 2024-10-24T10:09:34+00:00 Herve Codina herve.codina@bootlin.com 2024-10-14T12:46:33+00:00 eba0dedd27f9ad454deb580a1d09d63aa1766293 The sparx5 reset controller depends on the SPARX5 architecture or the LAN966x SoC. This reset controller can be used by the LAN966x PCI device and so it needs to be available when the LAN966x PCI device is enabled. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20241014124636.24221-5-herve.codina@bootlin.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
The sparx5 reset controller depends on the SPARX5 architecture or the
LAN966x SoC.

This reset controller can be used by the LAN966x PCI device and so it
needs to be available when the LAN966x PCI device is enabled.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20241014124636.24221-5-herve.codina@bootlin.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
reset: npcm: register npcm8xx clock auxiliary bus device 2024-10-17T22:17:51+00:00 Tomer Maimon tmaimon77@gmail.com 2024-09-12T19:10:37+00:00 22823157d90c4631a951920090686c20c459b36f Add NPCM8xx clock controller auxiliary bus device registration. The NPCM8xx clock controller is registered as an aux device because the reset and the clock controller share the same register region. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Benjamin Fair <benjaminfair@google.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20240912191038.981105-3-tmaimon77@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Add NPCM8xx clock controller auxiliary bus device registration.

The NPCM8xx clock controller is registered as an aux device because the
reset and the clock controller share the same register region.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Tested-by: Benjamin Fair <benjaminfair@google.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20240912191038.981105-3-tmaimon77@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
reset: amlogic: move drivers to a dedicated directory 2024-10-01T08:40:32+00:00 Jerome Brunet jbrunet@baylibre.com 2024-09-10T16:32:49+00:00 2c138ee3354f8088769d05701a2e16d1cb4cc22d The meson reset driver will be split in two part, one implemeting the ops, the other providing the platform driver support. This will be done to facilitate the addition of the auxiliary bus support. To avoid making a mess in drivers/reset/ while doing so, move the amlogic reset drivers to a dedicated directory. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20240910-meson-rst-aux-v5-7-60be62635d3e@baylibre.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
The meson reset driver will be split in two part, one implemeting the ops,
the other providing the platform driver support. This will be done to
facilitate the addition of the auxiliary bus support.

To avoid making a mess in drivers/reset/ while doing so, move the amlogic
reset drivers to a dedicated directory.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20240910-meson-rst-aux-v5-7-60be62635d3e@baylibre.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
reset: amlogic: convert driver to regmap 2024-10-01T08:40:32+00:00 Jerome Brunet jbrunet@baylibre.com 2024-09-10T16:32:43+00:00 7af26f3c11640c0ca3bd478e46454f4ec0cfc96a To allow using the same driver for the main reset controller and the auxiliary ones embedded in the clock controllers, convert the the Amlogic reset driver to regmap. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20240910-meson-rst-aux-v5-1-60be62635d3e@baylibre.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
To allow using the same driver for the main reset controller and the
auxiliary ones embedded in the clock controllers, convert the
the Amlogic reset driver to regmap.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20240910-meson-rst-aux-v5-1-60be62635d3e@baylibre.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>