linux.git/drivers/pinctrl, branch v4.3-rc1

Merge tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2015-09-04T17:22:09+00:00

Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.3 development
cycle.

Like with GPIO it's a lot of stuff. If my subsystems are any sign of
the overall tempo of the kernel v4.3 will be a gigantic diff.

[ It looks like 4.3 is calmer than 4.2 in most other subsystems, but
we'll see - Linus ]

Core changes:

- It is possible configure groups in debugfs.

- Consolidation of chained IRQ handler install/remove replacing all
call sites where irq_set_handler_data() and
irq_set_chained_handler() were done in succession with a combined
call to irq_set_chained_handler_and_data(). This series was
created by Thomas Gleixner after the problem was observed by
Russell King.

- Tglx also made another series of patches switching
__irq_set_handler_locked() for irq_set_handler_locked() which is
way cleaner.

- Tglx also wrote a good bunch of patches to make use of
irq_desc_get_xxx() accessors and avoid looking up irq_descs from
IRQ numbers. The goal is to get rid of the irq number from the
handlers in the IRQ flow which is nice.

Driver feature enhancements:

- Power management support for the SiRF SoC Atlas 7.

- Power down support for the Qualcomm driver.

- Intel Cherryview and Baytrail: switch drivers to use raw spinlocks
in IRQ handlers to play nice with the realtime patch set.

- Rework and new modes handling for Qualcomm SPMI-MPP.

- Pinconf power source config for SH PFC.

New drivers and subdrivers:

- A new driver for Conexant Digicolor CX92755.

- A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5,
ProXtream2 and PH1-LD6b SoC pin control support.

- Reverse-egineered the S/PDIF settings for the Allwinner sun4i
driver.

- Support for Qualcomm Technologies QDF2xxx ARM64 SoCs

- A new Freescale i.mx6ul subdriver.

Cleanup:

- Remove platform data support in a number of SH PFC subdrivers"

* tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits)
pinctrl: at91: fix null pointer dereference
pinctrl: mediatek: Implement wake handler and suspend resume
pinctrl: mediatek: Fix multiple registration issue.
pinctrl: sh-pfc: r8a7794: add USB pin groups
pinctrl: at91: Use generic irq_{request,release}_resources()
pinctrl: cherryview: Use raw_spinlock for locking
pinctrl: baytrail: Use raw_spinlock for locking
pinctrl: imx6ul: Remove .owner field
pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp
pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching
clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks
pinctrl: sun4i: add spdif to pin description.
pinctrl: atlas7: clear ugly branch statements for pull and drivestrength
pinctrl: baytrail: Serialize all register access
pinctrl: baytrail: Drop FSF mailing address
pinctrl: rockchip: only enable gpio clock when it setting
pinctrl/mediatek: fix spelling mistake in dev_err error message
pinctrl: cherryview: Serialize all register access
pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting
pinctrl: nomadik: reflect current input value
...

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

2015-09-01T20:09:20+00:00

Pull ARM DT updates from Olof Johansson:
 "Ladies and gentlemen, we proudly announce to you the latest branch of
  ARM device tree contents for the mainline kernel.  Come and see, come
  and see!

  No less than twentythree thousand lines of additions! Just imagine the
  joy you will have of using your mainline kernel on newly supported
  hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or
  UniPhier hardware!

  For those of you feeling less adventurous, added hardware support on
  platforms such as TI DM814x and Gumstix Overo platforms might be more
  of your liking.

  We've got something for everyone here!

  Ahem.  Cough.  So, anyway...

  This is the usual large batch of DT updates.  Lots and lots of smaller
  changes, some of the larger ones to point out are:

   - Rockchip veyron (Chromebook) support, as well as several other new boards
   - DRM support on Atmel AT91SAM9N12EK
   - USB additions on some Allwinner platforms
   - Mediatek MT6580 support
   - Freescale i.MX6UL support
   - cleanups for Renesas shmobile platforms
   - lots of added devices on LPC18xx
   - lots of added devices and boards on UniPhier

  There's also some dependent code added here, in particular some
  branches that are primarily merged through the clock tree"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits)
  ARM: tegra: Add gpio-ranges property
  ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114
  ARM: tegra: Add Tegra124 PMU support
  ARM: tegra: jetson-tk1: Add GK20A GPU DT node
  ARM: tegra: venice2: Add GK20A GPU DT node
  ARM: tegra: Add IOMMU node to GK20A
  ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
  ARM: tegra: Add entries for cpufreq on Tegra124
  ARM: tegra: Enable the DFLL on the Jetson TK1
  ARM: tegra: Add the DFLL to Tegra124 device tree
  ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
  ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
  ARM: dts: rockchip: correct regulator power states for suspend
  ARM: dts: rockchip: correct regulator PM properties
  ARM: dts: vexpress: Use assigned-clock-parents for sp810
  pinctrl: tegra: Only set the gpio range if needed
  arm: boot: dts: am4372: add ARM timers and SCU nodes
  ARM: dts: AM4372: Add the am4372-rtc compatible string
  ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
  ...

pinctrl: at91: fix null pointer dereference

2015-08-30T19:58:53+00:00

Not all gpio banks are necessarily enabled, in the current code this can
lead to null pointer dereferences.

[   51.130000] Unable to handle kernel NULL pointer dereference at virtual address 00000058
[   51.130000] pgd = dee04000
[   51.130000] [00000058] *pgd=3f66d831, *pte=00000000, *ppte=00000000
[   51.140000] Internal error: Oops: 17 [#1] ARM
[   51.140000] Modules linked in:
[   51.140000] CPU: 0 PID: 1664 Comm: cat Not tainted 4.1.1+ #6
[   51.140000] Hardware name: Atmel SAMA5
[   51.140000] task: df6dd880 ti: dec60000 task.ti: dec60000
[   51.140000] PC is at at91_pinconf_get+0xb4/0x200
[   51.140000] LR is at at91_pinconf_get+0xb4/0x200
[   51.140000] pc : []    lr : []    psr: 600f0013
sp : dec61e48  ip : 600f0013  fp : df522538
[   51.140000] r10: df52250c  r9 : 00000058  r8 : 00000068
[   51.140000] r7 : 00000000  r6 : df53c910  r5 : 00000000  r4 : dec61e7c
[   51.140000] r3 : 00000000  r2 : c06746d4  r1 : 00000000  r0 : 00000003
[   51.140000] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
[   51.140000] Control: 10c53c7d  Table: 3ee04059  DAC: 00000015
[   51.140000] Process cat (pid: 1664, stack limit = 0xdec60208)
[   51.140000] Stack: (0xdec61e48 to 0xdec62000)
[   51.140000] 1e40:                   00000358 00000000 df522500 ded15f80 c05a9d08 ded15f80
[   51.140000] 1e60: 0000048c 00000061 df522500 ded15f80 c05a9d08 c01e7304 ded15f80 00000000
[   51.140000] 1e80: c01e6008 00000060 0000048c c01e6034 c01e5f6c ded15f80 dec61ec0 00000000
[   51.140000] 1ea0: 00020000 ded6f280 dec61f80 00000001 00000001 c00ae0b8 b6e80000 ded15fb0
[   51.140000] 1ec0: 00000000 00000000 df4bc974 00000055 00000800 ded6f280 b6e80000 ded6f280
[   51.140000] 1ee0: ded6f280 00020000 b6e80000 00000000 00020000 c0090dec c0671e1c dec61fb0
[   51.140000] 1f00: b6f8b510 00000001 00004201 c000924c 00000000 00000003 00000003 00000000
[   51.140000] 1f20: df4bc940 00022000 00000022 c066e188 b6e7f000 c00836f4 000b6e7f ded6f280
[   51.140000] 1f40: ded6f280 b6e80000 dec61f80 ded6f280 00020000 c0091508 00000000 00000003
[   51.140000] 1f60: 00022000 00000000 00000000 ded6f280 ded6f280 00020000 b6e80000 c0091d9c
[   51.140000] 1f80: 00000000 00000000 ffffffff 00020000 00020000 b6e80000 00000003 c000f124
[   51.140000] 1fa0: dec60000 c000efa0 00020000 00020000 00000003 b6e80000 00020000 000271c4
[   51.140000] 1fc0: 00020000 00020000 b6e80000 00000003 7fffe000 00000000 00000000 00020000
[   51.140000] 1fe0: 00000000 bef50b64 00013835 b6f29c76 400f0030 00000003 00000000 00000000
[   51.140000] [] (at91_pinconf_get) from [] (at91_pinconf_dbg_show+0x18/0x2c0)
[   51.140000] [] (at91_pinconf_dbg_show) from [] (pinconf_pins_show+0xc8/0xf8)
[   51.140000] [] (pinconf_pins_show) from [] (seq_read+0x1a0/0x464)
[   51.140000] [] (seq_read) from [] (__vfs_read+0x20/0xd0)
[   51.140000] [] (__vfs_read) from [] (vfs_read+0x7c/0x108)
[   51.140000] [] (vfs_read) from [] (SyS_read+0x40/0x94)
[   51.140000] [] (SyS_read) from [] (ret_fast_syscall+0x0/0x3c)
[   51.140000] Code: eb010ec2 e30a0d08 e34c005a eb0ae5a7 (e5993000)
[   51.150000] ---[ end trace fb3c370da3ea4794 ]---

Fixes: a0b957f306fa ("pinctrl: at91: allow to have disabled gpio bank")
Cc: stable@vger.kernel.org # 3.18
Signed-off-by: David Dueck 
Acked-by: Ludovic Desroches 
Acked-by: Alexandre Belloni 
Acked-by: Nicolas Ferre 
Cc: Boris Brezillon 
Cc: Jean-Christophe PLAGNIOL-VILLARD 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Linus Walleij

pinctrl: mediatek: Implement wake handler and suspend resume

2015-08-26T12:39:43+00:00

This patch implement irq_set_wake to get who is wakeup source and
setup on suspend resume.

Signed-off-by: Maoguang Meng 
Reviewed-by: Daniel Kurtz 
Acked-by: Yingjoe Chen 
Acked-by: Hongzhou Yang 
Signed-off-by: Linus Walleij

pinctrl: mediatek: Fix multiple registration issue.

2015-08-26T12:37:44+00:00

Since our common driver need support main chip and PMU
at the same time, that means it will register two
pinctrl device, and the pinctrl_desc structure should
be used two times.

But pinctrl_desc use global static definition, then
the latest registered pinctrl device will overwrite
the old one's, all members in pinctrl_desc will set to
the new one's, such as name, pins and pins numbers, etc.
This is a bug.

Move pinctrl_desc into mtk_pinctrl, assign new value for
each pinctrl device to fix it.

Cc: stable@vger.kernel.org # v4.1+
Signed-off-by: Hongzhou Yang 
Reviewed-by: Axel Lin 
Signed-off-by: Linus Walleij

pinctrl: sh-pfc: r8a7794: add USB pin groups

2015-08-26T11:40:25+00:00

Add USB0/1 pin groups to R8A7794 PFC driver.

Signed-off-by: Shinobu Uehara 
[Sergei: rebased, renamed, added changelog.]
Signed-off-by: Sergei Shtylyov 
Acked-by: Laurent Pinchart 
Signed-off-by: Linus Walleij

pinctrl: at91: Use generic irq_{request,release}_resources()

2015-08-26T07:32:20+00:00

The at91-specific irq_{request,release}_resources() callbacks are
identical to the generic ones, modulo the bug fix in 5b76e79c77264899
("gpiolib: irqchip: prevent driver unloading if gpio is used as irq
only").

Until commit 8b67a1f0ad1f260f ("gpio: don't override irq_*_resources()
callbacks"), the buggy at91-specific callbacks were never used, though.

Hence drop the at91-specific ones in favor of the generic ones.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Linus Walleij

pinctrl: cherryview: Use raw_spinlock for locking

2015-08-26T07:27:39+00:00

When running -rt kernel and an interrupt happens on a GPIO line controlled by
Intel Cherryview/Braswell pinctrl driver we get:

 BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917
 in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0
 Preemption disabled at:[] cpu_startup_entry+0x17f/0x480

 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.5-rt5 #16
  ...
 Call Trace:
    [] dump_stack+0x4a/0x61
  [] ___might_sleep+0xe7/0x170
  [] rt_spin_lock+0x1f/0x50
  [] chv_gpio_irq_ack+0x3d/0xa0
  [] handle_edge_irq+0x75/0x180
  [] generic_handle_irq+0x27/0x40
  [] chv_gpio_irq_handler+0x7e/0x110
  [] handle_irq+0xaa/0x190
  ...

This is because desc->lock is raw_spinlock and is held when chv_gpio_irq_ack()
is called by the genirq core. chv_gpio_irq_ack() in turn takes pctrl->lock
which in -rt is an rt-mutex causing might_sleep() rightfully to complain about
sleeping function called from invalid context.

In order to keep -rt happy but at the same time make sure that register
accesses get serialized, convert the driver to use raw_spinlock instead.

Suggested-by: Linus Walleij 
Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij

pinctrl: baytrail: Use raw_spinlock for locking

2015-08-26T07:25:33+00:00

The Intel Baytrail pinctrl driver implements irqchip callbacks which are
called with desc->lock raw_spinlock held. In mainline this is fine because
spinlock resolves to raw_spinlock. However, running the same code in -rt we
get:

 BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917
 in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0
 Preemption disabled at:[] cpu_startup_entry+0x17f/0x480

 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.5-rt5 #13
  ...
 Call Trace:
    [] dump_stack+0x4a/0x61
  [] ___might_sleep+0xe7/0x170
  [] rt_spin_lock+0x1f/0x50
  [] byt_gpio_clear_triggering+0x38/0x60
  [] byt_irq_mask+0x11/0x20
  [] handle_level_irq+0x83/0x150
  [] generic_handle_irq+0x27/0x40
  [] byt_gpio_irq_handler+0x7f/0xc0
  [] handle_irq+0xaa/0x190
  ...

This is because in -rt spinlocks are preemptible so taking the driver
private spinlock in irqchip callbacks causes might_sleep() to trigger.

In order to keep -rt happy but at the same time make sure that register
accesses get serialized, convert the driver to use raw_spinlock instead.

Also shorten the critical section a bit in few places.

Suggested-by: Linus Walleij 
Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij

pinctrl: imx6ul: Remove .owner field

2015-08-25T14:29:06+00:00

platform_driver does not need to set an owner as it will be
populated by the driver core.

The semantic patch that makes this change is available
in scripts/coccinelle/api/platform_no_drv_owner.cocci.

Signed-off-by: Fabio Estevam 
Signed-off-by: Linus Walleij