linux.git/drivers/pinctrl/renesas, branch v6.8

Merge tag 'renesas-pinctrl-for-v6.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

2023-12-18T14:06:18+00:00

pinctrl: renesas: Updates for v6.8 (take two)

  - Add pinmux groups, power source, and input/output enable support for
    Ethernet pins on RZ/G2L SoCs,
  - Miscellaneous fixes and improvements.

Signed-off-by: Linus Walleij

pinctrl: renesas: rzg2l: Add input enable to the Ethernet pins

2023-12-15T10:34:34+00:00

Some of the RZ/G3S Ethernet pins (P1_0, P7_0) can be configured with
input enable.  Enable this functionality for these pins.

Signed-off-by: Claudiu Beznea 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/r/20231207070700.4156557-8-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

pinctrl: renesas: rzg2l: Add output enable support

2023-12-15T10:34:34+00:00

Some of the Ethernet pins on RZ/G3S (but also valid for RZ/G2L) need to
have the direction of the IO buffer set as output for Ethernet to work
properly.  On RZ/G3S, these pins are P1_0/P7_0, P1_1/P7_1, and can have
the following Ethernet functions: TXC/TX_CLK or TX_CTL/TX_EN.

As the pins supporting output enable are SoC specific, and there is a
limited number of these pins (TXC/TX_CLK and/or TX_CTL/TX_EN), specify
output enable capable port limits in the platform-based configuration
data structure, to ensure proper validation.

The OEN support has been intantiated for RZ/G3S at the moment.

Signed-off-by: Claudiu Beznea 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/r/20231207070700.4156557-7-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

pinctrl: renesas: rzg2l: Add support to select power source for Ethernet pins

2023-12-15T10:34:34+00:00

The GPIO controller available on RZ/G3S (but also on RZ/G2L) supports
setting the power source for Ethernet pins.  Based on the interface b/w
the Ethernet controller and the Ethernet PHY, and on board design, a
specific power source needs to be selected.  The GPIO controller
supports 1.8V, 2.5V, and 3.3V power source selection for the Ethernet
pins.  This can be selected though the ETHx_POC registers (x={0, 1}).

Adjust the driver to support this, and to do proper instantiation for
the RZ/G3S and RZ/G2L SoCs.  On RZ/G2L only the get operation has been
tested at the moment.

While at it, as the power registers on RZ/G2L support access sizes of 8
bits, and these registers on RZ/G3S support access sizes of 8/16/32
bits, replace writel()/readl() on these registers with writeb()/readb().
This should allow us to use the same code on both SoCs w/o any issues.

Signed-off-by: Claudiu Beznea 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/r/20231207070700.4156557-6-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups

2023-12-15T10:34:34+00:00

On RZ/G3S different Ethernet pins need to be configured with different
settings (e.g. power-source needs to be set, RGMII TXC and TX_CTL pins
need output-enable).  Adjust the driver to allow specifying pin
configuration for pinmux groups.  With this, DT settings like the
following are taken into account by the driver:

    eth0_pins: eth0 {
	    tx_ctl {
		    pinmux = ;  /* ET0_TX_CTL */
		    power-source = <1800>;
		    output-enable;
		    drive-strength-microamp = <5200>;
	    };
    };

Signed-off-by: Claudiu Beznea 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/r/20231207070700.4156557-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

pinctrl: renesas: rzg2l: Move arg and index in the main function block

2023-12-13T18:37:57+00:00

Move arg and index in the main block of the function as they are used by
more than one case block of switch-case (3 out of 4 for arg, 2 out of 4
for index). In this way some lines of code are removed.

Signed-off-by: Claudiu Beznea 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/r/20231207070700.4156557-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

pinctrl: renesas: Convert to use grp member

2023-12-11T23:47:52+00:00

Convert drivers to use grp member embedded in struct group_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin group description.

Reviewed-by: Geert Uytterhoeven 
Acked-by: Geert Uytterhoeven 
Signed-off-by: Andy Shevchenko 
Link: https://lore.kernel.org/r/20231211190321.307330-12-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij

pinctrl: renesas: Mark local variable with const in ->set_mux()

2023-12-07T09:53:57+00:00

We are not going to change pins in the ->set_mux() callback. Mark
the local variable with a const qualifier. While at it, make it
also unsigned.

Signed-off-by: Andy Shevchenko 
Reviewed-by: Geert Uytterhoeven 
Acked-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/r/20231204160033.1872569-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij

pinctrl: renesas: rzg2l: Enhance driver to support interrupt affinity setting

2023-11-27T10:11:22+00:00

Implement irq_set_affinity callback so that we can set affinity
for GPIO IRQs.

Signed-off-by: Lad Prabhakar 
Reviewed-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/r/20231011195923.67404-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven

treewide: rename pinctrl_gpio_direction_output_new()

2023-11-04T09:23:22+00:00

Now that pinctrl_gpio_direction_output() is no longer used, let's drop
the '_new' suffix from its improved variant.

Signed-off-by: Bartosz Golaszewski 
Acked-by: Linus Walleij