<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/pinctrl/ralink, branch v5.11</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>pinctrl: ralink: add a pinctrl driver for the rt2880 family</title>
<updated>2020-12-08T08:58:01+00:00</updated>
<author>
<name>Sergio Paracuellos</name>
<email>sergio.paracuellos@gmail.com</email>
</author>
<published>2020-12-08T07:55:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=518b466a21ad7fa1e338fa4ed9d180ef439d3bc0'/>
<id>518b466a21ad7fa1e338fa4ed9d180ef439d3bc0</id>
<content type='text'>
These Socs have 1-3 banks of 8-32 gpios. Rather then setting the muxing of each
pin individually, these socs have mux groups that when set will effect 1-N pins.
Pin groups have a 2, 4 or 8 different muxes.

Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Sergio Paracuellos &lt;sergio.paracuellos@gmail.com&gt;
Link: https://lore.kernel.org/r/20201208075523.7060-3-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
These Socs have 1-3 banks of 8-32 gpios. Rather then setting the muxing of each
pin individually, these socs have mux groups that when set will effect 1-N pins.
Pin groups have a 2, 4 or 8 different muxes.

Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Sergio Paracuellos &lt;sergio.paracuellos@gmail.com&gt;
Link: https://lore.kernel.org/r/20201208075523.7060-3-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
