linux.git/drivers/pinctrl/qcom, branch v5.9-rc2

Merge tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2020-08-09T19:52:28+00:00

Pull pin control updates from Linus Walleij:
"This is the bulk of the pin control changes for the v5.9 kernel
series:

Core changes:

- The GPIO patch "gpiolib: Introduce for_each_requested_gpio_in_range()
macro" was put in an immutable branch and merged into the pinctrl
tree as well. We see these changes also here.

- Improved debug output for pins used as GPIO.

New drivers:

- Ocelot Sparx5 SoC driver.

- Intel Emmitsburg SoC subdriver.

- Intel Tiger Lake-H SoC subdriver.

- Qualcomm PM660 SoC subdriver.

- Renesas SH-PFC R8A774E1 subdriver.

Driver improvements:

- Linear improvement and cleanups of the Intel drivers for
Cherryview, Lynxpoint, Baytrail etc. Improved locking among other
things.

- Renesas SH-PFC has added support for RPC pins, groups, and
functions to r8a77970 and r8a77980.

- The newere Freescale (now NXP) i.MX8 pin controllers have been
modularized. This is driven by the Google Android GKI initiative I
think.

- Open drain support for pins on the Qualcomm IPQ4019.

- The Ingenic driver can handle both edges IRQ detection.

- A big slew of documentation fixes all over the place.

- A few irqchip template conversions by yours truly.

* tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits)
dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
pinctrl: stmfx: Use irqchip template
pinctrl: amd: Use irqchip template
pinctrl: mediatek: fix build for tristate changes
pinctrl: samsung: Use bank name as irqchip name
pinctrl: core: print gpio in pins debugfs file
pinctrl: mediatek: add mt6779 eint support
pinctrl: mediatek: add pinctrl support for MT6779 SoC
pinctrl: mediatek: avoid virtual gpio trying to set reg
pinctrl: mediatek: update pinmux definitions for mt6779
pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API
pinctrl: mcp23s08: Use irqchip template
pinctrl: sx150x: Use irqchip template
dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodes
pinctrl: intel: Add Intel Emmitsburg pin controller support
pinctl: ti: iodelay: Replace HTTP links with HTTPS ones
Revert "gpio: omap: handle pin config bias flags"
pinctrl: single: Use fallthrough pseudo-keyword
pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword
pinctrl: baytrail: Use fallthrough pseudo-keyword
...

Merge tag 'pinctrl-v5.8-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2020-08-01T17:11:42+00:00

Pull pin control fix from Linus Walleij:
 "A single last minute pin control fix to the Qualcomm driver fixing
  missing dual edge PCH interrupts"

* tag 'pinctrl-v5.8-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: qcom: Handle broken/missing PDC dual edge IRQs on sc7180

pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword

2020-07-20T13:38:27+00:00

Replace the existing /* fall through */ comments and its variants with
the new pseudo-keyword macro fallthrough[1].

[1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through

Signed-off-by: Gustavo A. R. Silva 
Link: https://lore.kernel.org/r/20200716212213.GA17623@embeddedor
Signed-off-by: Linus Walleij

pinctrl: qcom: Handle broken/missing PDC dual edge IRQs on sc7180

2020-07-16T13:41:41+00:00

Depending on how you look at it, you can either say that:
a) There is a PDC hardware issue (with the specific IP rev that exists
   on sc7180) that causes the PDC not to work properly when configured
   to handle dual edges.
b) The dual edge feature of the PDC hardware was only added in later
   HW revisions and thus isn't in all hardware.

Regardless of how you look at it, let's work around the lack of dual
edge support by only ever letting our parent see requests for single
edge interrupts on affected hardware.

NOTE: it's possible that a driver requesting a dual edge interrupt
might get several edges coalesced into a single IRQ.  For instance if
a line starts low and then goes high and low again, the driver that
requested the IRQ is not guaranteed to be called twice.  However, it
is guaranteed that once the driver's interrupt handler starts running
its first instruction that any new edges coming in will cause the
interrupt to fire again.  This is relatively commonplace for dual-edge
gpio interrupts (many gpio controllers require software to emulate
dual edge with single edge) so client drivers should be setup to
handle it.

Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy")
Signed-off-by: Douglas Anderson 
Reviewed-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20200714080254.v3.1.Ie0d730120b232a86a4eac1e2909bcbec844d1766@changeid
Signed-off-by: Linus Walleij

pinctrl: qcom: pinctrl-msm8976: Remove unused variable 'nav_tsync_groups'

2020-07-16T13:12:38+00:00

Fixes the following W=1 kernel build warning(s):

 drivers/pinctrl/qcom/pinctrl-msm8976.c:802:27: warning: ‘nav_tsync_groups’ defined but not used [-Wunused-const-variable=]
 802 | static const char
 const nav_tsync_groups[] = {
 | ^~~~~~~~~~~~~~~~

Signed-off-by: Lee Jones 
Cc: Andy Gross 
Cc: Bjorn Andersson 
Cc: Del Regno 
Cc: linux-arm-msm@vger.kernel.org
Link: https://lore.kernel.org/r/20200713144930.1034632-10-lee.jones@linaro.org
Signed-off-by: Linus Walleij

pinctrl: qcom: pinctrl-msm: Complete 'struct msm_pinctrl' documentation

2020-07-16T13:12:38+00:00

Add missing descriptions for attributes and fix 1 formatting issue.

Fixes the following W=1 kernel build warning(s):

 drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'desc' not described in 'msm_pinctrl'
 drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'irq_chip' not described in 'msm_pinctrl'
 drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'intr_target_use_scm' not described in 'msm_pinctrl'
 drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'soc' not described in 'msm_pinctrl'
 drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'phys_base' not described in 'msm_pinctrl'

Signed-off-by: Lee Jones 
Cc: Bjorn Andersson 
Cc: Andy Gross 
Cc: linux-arm-msm@vger.kernel.org
Link: https://lore.kernel.org/r/20200713144930.1034632-6-lee.jones@linaro.org
Signed-off-by: Linus Walleij

pinctrl: qcom: ipq4019: add open drain support

2020-07-16T08:46:24+00:00

[ Brian: adapted from from the Chromium OS kernel used on IPQ4019-based
  WiFi APs. ]

Signed-off-by: Jaiganesh Narayanan 
Signed-off-by: Brian Norris 
Link: https://lore.kernel.org/r/20200703080646.23233-1-computersforpeace@gmail.com
Signed-off-by: Linus Walleij

pinctrl: qcom: ipq8074: route gpio interrupts to APPS

2020-07-11T21:11:00+00:00

set target proc as APPS to route the gpio interrupts to APPS

Co-developed-by: Rajkumar Ayyasamy 
Signed-off-by: Rajkumar Ayyasamy 
Signed-off-by: Kathiravan T 
Acked-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/1594107588-17055-1-git-send-email-kathirav@codeaurora.org
Signed-off-by: Linus Walleij

pinctrl: qcom: spmi-gpio: Add pm660(l) compatibility

2020-07-07T12:01:24+00:00

Add support for pm660(l) SPMI GPIOs. The PMICs feature
13 and 12 GPIOs respectively, though with a lot of
holes inbetween.

Signed-off-by: Konrad Dybcio 
Acked-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20200622192558.152828-2-konradybcio@gmail.com
Signed-off-by: Linus Walleij

pinctrl: qcom: ipq6018 Add missing pins in qpic pin group

2020-06-20T20:05:24+00:00

The patch adds missing qpic data pins to qpic pingroup. These pins are
necessary for the qpic nand to work.

Fixes: ef1ea54eab0e ("pinctrl: qcom: Add ipq6018 pinctrl driver")
Signed-off-by: Sivaprakash Murugesan 
Link: https://lore.kernel.org/r/1592541089-17700-1-git-send-email-sivaprak@codeaurora.org
Signed-off-by: Linus Walleij