linux.git/drivers/pinctrl/meson, branch v4.16 Linux kernel source tree pinctrl: meson-axg: adjust uart_ao_b pin group naming 2018-02-12T09:47:36+00:00 Yixun Lan yixun.lan@amlogic.com 2018-01-18T14:17:57+00:00 49527bc0e8d207e87bf3ebe8eb8cce7353372d79 Simply adjust the pin group to _x _y _z style, as to keep the consistency in DT with previous naming scheme. Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC") Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Simply adjust the pin group to _x _y _z style, as to
keep the consistency in DT with previous naming scheme.

Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC")
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson-axg: adjust spicc pin naming 2017-12-12T23:52:49+00:00 Yixun Lan yixun.lan@amlogic.com 2017-12-08T15:29:09+00:00 d72ebbcc446086cbc1116f83d6da063b2dc24fe4 According to datasheet, we should use numbers for the pin naming instead of letters. The patch here try to fix this to keep the consistency. This patch should not bring any functional change. Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC") Suggested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
According to datasheet, we should use numbers for the pin naming
instead of letters. The patch here try to fix this to keep
the consistency.

This patch should not bring any functional change.

Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC")
Suggested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC 2017-11-30T13:29:38+00:00 Xingyu Chen xingyu.chen@amlogic.com 2017-11-20T10:08:25+00:00 83c566806a68a4b68cb87f5c605b8286d0b9f7a0 Add new pinctrl driver for Amlogic's Meson-AXG SoC. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add new pinctrl driver for Amlogic's Meson-AXG SoC.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson-axg: Introduce a pinctrl pinmux ops for Meson-AXG SoC 2017-11-30T13:28:16+00:00 Xingyu Chen xingyu.chen@amlogic.com 2017-11-20T10:08:24+00:00 0fabe43f3f60e151e4a266049de66aa1fb4e2146 The pin controller has been updated in the Amlogic Meson AXG series, which use continuous 4-bit register to select function for each pin. In order to support this, a new pinmux operations "meson_axg_pmx_ops" has been added. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
The pin controller has been updated in the Amlogic Meson AXG series,
which use continuous 4-bit register to select function for each pin.
In order to support this, a new pinmux operations "meson_axg_pmx_ops"
has been added.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson: rework pinmux ops 2017-10-16T21:14:10+00:00 Jerome Brunet jbrunet@baylibre.com 2017-10-12T12:40:26+00:00 ce385aa24a0dcccdc81dfcbc90cf7aa290d8b758 This change prepare the introduction of new meson SoC. This new SoC will share the same gpio/pinconf registers but the pinmux part will be different. While the format of the data associated with each pinmux group will change, the way to handle pinmuxing will be similar. To deal with this new situation, the meson_pmx_struture is kept but the data associated to it is now generic. This allows to reuse the basic functions which would otherwise be copy/pasted in each pinmux driver (such as getting the name a count of groups and functions) Only the functions actually using this specific data is taken out of the common code and is handling the SoC pinmuxing Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
This change prepare the introduction of new meson SoC. This new SoC will
share the same gpio/pinconf registers but the pinmux part will be
different. While the format of the data associated with each pinmux group
will change, the way to handle pinmuxing will be similar.

To deal with this new situation, the meson_pmx_struture is kept but the
data associated to it is now generic. This allows to reuse the basic
functions which would otherwise be copy/pasted in each pinmux driver
(such as getting the name a count of groups and functions) Only the
functions actually using this specific data is taken out of the common
code and is handling the SoC pinmuxing

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson: separate soc drivers 2017-10-16T21:14:10+00:00 Jerome Brunet jbrunet@baylibre.com 2017-10-12T12:40:25+00:00 277d14eb815fdfb95a72ea126bc09f75a2bd58fd When meson pinctrl is enabled, all meson platforms pinctrl drivers are built in the kernel, with a significant amount of data. This leads to situation where pinctrl drivers targeting an architecture are also compiled and shipped on another one (ex: meson8 - ARM - compiled and shipped on ARM64 builds). This is a waste of memory we can easily avoid. This change makes 4 pinctrl drivers (1 per SoC) out the original single driver, allowing to compile and ship only the ones required. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
When meson pinctrl is enabled, all meson platforms pinctrl drivers are
built in the kernel, with a significant amount of data.

This leads to situation where pinctrl drivers targeting an architecture
are also compiled and shipped on another one (ex: meson8 - ARM - compiled
and shipped on ARM64 builds). This is a waste of memory we can easily
avoid.

This change makes 4 pinctrl drivers (1 per SoC) out the original single
driver, allowing to compile and ship only the ones required.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson: remove unused pin_base 2017-10-11T07:54:14+00:00 Jerome Brunet jbrunet@baylibre.com 2017-10-06T08:54:07+00:00 6affd6981ca5d2b1d3d9d5191b18bd4a692587fe While removing the need to have pin_base defined in meson pinctrl drivers, I forgot to remove the corresponding field from the pinctrl_data structure. Fixing this now. Fixes: 70e5ecb1b994 ("pinctrl: meson: get rid of pin_base") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
While removing the need to have pin_base defined in meson pinctrl
drivers, I forgot to remove the corresponding field from the
pinctrl_data structure.

Fixing this now.

Fixes: 70e5ecb1b994 ("pinctrl: meson: get rid of pin_base")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson-gx: add TEST_N i2s pinmux 2017-10-11T07:53:00+00:00 Jerome Brunet jbrunet@baylibre.com 2017-10-06T08:31:42+00:00 d51b989b2b5fecd241c4e77952d664c34beaabf9 Add TEST_N pinmux for channel 6 and 7 of the i2s output Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add TEST_N pinmux for channel 6 and 7 of the i2s output

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson-gxbb: add missing GPIOX_22 pin 2017-10-05T21:11:02+00:00 Jerome Brunet jbrunet@baylibre.com 2017-09-20T13:39:27+00:00 027c87fe69599598c6d396b971d2cd9ef45e002e GPIOX_22 is declared as a gpio but the id is no present in the pin table. This hole trigger an error while reading the pingroup debugfs entry GPIOX_22 is no routed externally. For all we know, it could an internal pin of SoC Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
GPIOX_22 is declared as a gpio but the id is no present in the pin
table. This hole trigger an error while reading the pingroup debugfs entry

GPIOX_22 is no routed externally. For all we know, it could an internal
pin of SoC

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson-gx: TEST_N belongs to the AO controller 2017-10-05T21:11:02+00:00 Jerome Brunet jbrunet@baylibre.com 2017-09-20T13:39:26+00:00 e891a5a40103bc887befb21bbee83308e3669309 On meson-gx platforms, TEST_N has been incorrectly declared in the EE controller while it belongs to AO controller. Move the pin to the appropriate controller Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
On meson-gx platforms, TEST_N has been incorrectly declared in the EE
controller while it belongs to AO controller.

Move the pin to the appropriate controller

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>