linux.git/drivers/pinctrl/intel/pinctrl-intel.c, branch v4.14

pinctrl: intel: Read back TX buffer state

2017-08-31T13:34:31+00:00

In the same way as it's done in pinctrl-cherryview.c we would provide
a readback TX buffer state.

Fixes: 17fab473693 ("pinctrl: intel: Set pin direction properly")
Reported-by: "Bourque, Francis" 
Signed-off-by: Andy Shevchenko 
Acked-by: Mika Westerberg 
Tested-by: "Bourque, Francis" 
Signed-off-by: Linus Walleij

pinctrl: intel: Decrease indentation in intel_gpio_set()

2017-08-31T12:46:36+00:00

Decrease indentation in intel_gpio_set() to make it looking slightly better
and be in align with intel_gpio_get().

Signed-off-by: Andy Shevchenko 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij

pinctrl: intel: Disable GPIO pin interrupts in suspend

2017-08-22T12:46:15+00:00

The fix prevents unintended wakes from second level GPIO pin interrupts.

On some Intel Kabylake platforms, it is observed that GPIO pin interrupts
can wake the platform from suspend-to-idle, even though the IRQ is not
configured as IRQF_NO_SUSPEND or enable_irq_wake().

This can cause undesired wakes on Mobile devices such as Laptops and
Chromebook devices. For example a headset jack insertion is not a desired
wake source on Chromebook devices.

The pinctrl-intel (GPIO controller) driver implements a "Shared IRQ" model.
All GPIO pin interrupts are OR'ed and mapped to a first level IRQ14 (or
IRQ15). The driver registers an irq_chip struct and maps an irq_domain for
the GPIO pin interrupts. The IRQ14 handler demuxes and calls the second
level IRQ for the respective pin.

In the suspend entry flow, at suspend_noirq stage, the kernel disables IRQs
that are not marked for wake. The pinctrl-intel driver does not implement a
irq_disable()  callback (to take advantage of lazy disabling). The
pinctrl-intel GPIO interrupts are not disabled in hardware during suspend
entry, and thus are able to wake the SoC out of suspend-to-idle.

This patch sets the IRQCHIP_MASK_ON_SUSPEND flag for the GPIO irq_chip, to
disable the second level interrupts at suspend_noirq stage via the irq_mask
callbacks. The irq_mask callback disables the IRQs in hardware by
programming the corresponding GPIO pad registers. Only IRQs that are not
marked for wake are disabled.

Signed-off-by: Rushikesh S Kadam 
Acked-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
Reviewed-and-tested-by: Rajneesh Bhardwaj 
Signed-off-by: Linus Walleij

pinctrl: intel: Make it possible to specify mode per pin in a group

2017-06-09T11:02:50+00:00

On some SoCs not all pins in a group use the same mode when a certain
function is muxed out of them. This makes it possible to specify mode per
pin as an array instead in addition to single integer.

Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Linus Walleij

pinctrl: intel: Add support for variable size pad groups

2017-06-09T11:01:35+00:00

The Intel GPIO hardware has a concept of pad groups, which means 1 to 32
pads occupying their own GPI_IS, GPI_IE, PAD_OWN and so on registers. The
existing hardware has the same amount of pads in each pad group (except the
last one) so it is possible to use community->gpp_size to calculate start
offset of each register.

With the next generation SoCs the pad group size is not always the same
anymore which means we cannot use community->gpp_size for register offset
calculations directly.

To support variable size pad groups we introduce struct intel_padgroup that
can be filled in by the client drivers according the hardware pad group
layout. The core driver will always use these when it performs calculations
for pad register offsets. The core driver will automatically populate pad
groups based on community->gpp_size if the driver does not provide any.
This makes sure the existing drivers still work as expected.

Signed-off-by: Mika Westerberg 
Signed-off-by: Chuah, Kim Tatt 
Signed-off-by: Tan Jui Nee 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Linus Walleij

pinctrl: intel: unlock on error in intel_config_set_pull()

2017-02-13T14:42:26+00:00

We need to unlock before returning -EINVAL on this error path.

Fixes: 04cc058f0c52 ("pinctrl: intel: Add support for 1k additional pull-down")
Signed-off-by: Dan Carpenter 
Signed-off-by: Linus Walleij

pinctrl: intel: Add support for 1k additional pull-down

2017-01-30T14:04:23+00:00

The next generation Intel GPIO hardware supports additional 1k pull-down
per-pad. Add support for this to the Intel core pinctrl driver.

Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Linus Walleij

pinctrl: intel: Add support for hardware debouncer

2017-01-30T14:01:35+00:00

The next generation Intel GPIO hardware has two additional registers
PADCFG2 and PADCFG3. The latter is marked as reserved but the former
includes configuration for per-pad hardware debouncer.

This patch adds support for that in the Intel pinctrl core driver. Since
these are additional features on top of the current generation hardware,
we use revision number and feature flags to enable this if detected.

Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Linus Walleij

Merge tag 'v4.10-rc6' into devel

2017-01-30T13:39:20+00:00

Linux 4.10-rc6

Resolved conflicts in:
	drivers/pinctrl/pinctrl-amd.c
	drivers/pinctrl/samsung/pinctrl-exynos.c

pinctrl: intel: Convert to use devm_gpiochip_add_data()

2017-01-11T12:52:37+00:00

This simplifies error handling and allows us to drop intel_pinctrl_remove()
completely.

Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Linus Walleij