linux.git/drivers/pinctrl/aspeed, branch v7.2-rc2 Linux kernel source tree Replace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c files) 2026-07-03T05:38:17+00:00 Uwe Kleine-König (The Capable Hub) u.kleine-koenig@baylibre.com 2026-06-30T09:24:36+00:00 995832b2cebe6969d1b42635db698803ee31294d Replace the #include of <linux/mod_devicetable.h> by the more specific <linux/device-id/*.h> where applicable. For most cases the include can be dropped completely, only a few drivers need one or two headers added. Acked-by: Danilo Krummrich <dakr@kernel.org> Acked-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com> 
Replace the #include of <linux/mod_devicetable.h> by the more specific
<linux/device-id/*.h> where applicable. For most cases the include
can be dropped completely, only a few drivers need one or two headers
added.

Acked-by: Danilo Krummrich <dakr@kernel.org>
Acked-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com
Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
pinctrl: aspeed: Fix GPIO mux value for ADC-capable balls 2026-06-08T08:18:52+00:00 Billy Tsai billy_tsai@aspeedtech.com 2026-06-05T06:38:09+00:00 be3ee6e6710ee766448b55a6041e73a393cfff79 aspeed_g7_soc1_gpio_request_enable() unconditionally writes mux function 0 to route the requested pin to GPIO. This is wrong for the ADC-capable balls W17 through AB19 (ADC0-ADC15), where function 0 selects the ADC input and function 1 selects GPIO. Requesting one of those GPIOs therefore muxed the ball to ADC instead. Write mux value 1 for balls W17 through AB19 so the GPIO function is actually selected. Fixes: 4af4eb66aac3 ("pinctrl: aspeed: Add AST2700 SoC1 support") Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Signed-off-by: Linus Walleij <linusw@kernel.org> 
aspeed_g7_soc1_gpio_request_enable() unconditionally writes mux
function 0 to route the requested pin to GPIO. This is wrong for the
ADC-capable balls W17 through AB19 (ADC0-ADC15), where function 0
selects the ADC input and function 1 selects GPIO. Requesting one of
those GPIOs therefore muxed the ball to ADC instead.

Write mux value 1 for balls W17 through AB19 so the GPIO function is
actually selected.

Fixes: 4af4eb66aac3 ("pinctrl: aspeed: Add AST2700 SoC1 support")
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
pinctrl: aspeed: Add AST2700 SoC1 support 2026-05-25T08:04:32+00:00 Billy Tsai billy_tsai@aspeedtech.com 2026-05-21T09:17:46+00:00 4af4eb66aac382b08a8fcf822161f48cbed3aa08 Implement pin multiplexing (and pin configuration where applicable) for the AST2700 SoC1 SCU pinctrl block using static SoC data tables. Unlike legacy ASPEED pin controllers, the SoC1 pin function control fields are highly regular, which makes it practical to describe the packed-field register layout directly in driver data rather than reuse the existing Aspeed pinctrl macro infrastructure. The driver uses the generic pinctrl, pinmux and pinconf frameworks. The controller registers are accessed via regmap from the parent syscon, allowing shared ownership of the SCU register block. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Signed-off-by: Linus Walleij <linusw@kernel.org> 
Implement pin multiplexing (and pin configuration where applicable)
for the AST2700 SoC1 SCU pinctrl block using static SoC data tables.

Unlike legacy ASPEED pin controllers, the SoC1 pin function control
fields are highly regular, which makes it practical to describe the
packed-field register layout directly in driver data rather than reuse
the existing Aspeed pinctrl macro infrastructure.

The driver uses the generic pinctrl, pinmux and pinconf frameworks.
The controller registers are accessed via regmap from the parent
syscon, allowing shared ownership of the SCU register block.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
pinctrl: aspeed: Add AST2700 SoC0 support 2026-05-11T20:03:24+00:00 Billy Tsai billy_tsai@aspeedtech.com 2026-05-06T08:06:20+00:00 7f73aa118a6fd9d3a8a2030e1f6aa0dd5dc8cae1 Add pinctrl support for the SoC0 instance of the ASPEED AST2700. AST2700 consists of two interconnected SoC instances, each with its own pinctrl register block. The SoC0 pinctrl hardware closely follows the design found in previous ASPEED BMC generations, allowing the driver to build upon the common ASPEED pinctrl infrastructure. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Signed-off-by: Linus Walleij <linusw@kernel.org> 
Add pinctrl support for the SoC0 instance of the ASPEED AST2700.

AST2700 consists of two interconnected SoC instances, each with its own
pinctrl register block.

The SoC0 pinctrl hardware closely follows the design found in previous
ASPEED BMC generations, allowing the driver to build upon the common
ASPEED pinctrl infrastructure.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
pinctrl: aspeed: Cleanup header includes 2026-01-19T00:11:46+00:00 Krzysztof Kozlowski krzysztof.kozlowski@oss.qualcomm.com 2026-01-18T18:09:24+00:00 a7f7ee348de1b4ef2d5d328517984a965245ac9f Remove unused includes (no mutexes, string functions, no OF functions) and bring directly used mod_devicetable.h (previously pulled via of.h). Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org> 
Remove unused includes (no mutexes, string functions, no OF functions)
and bring directly used mod_devicetable.h (previously pulled via of.h).

Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
pinctrl: aspeed: g5: Constrain LPC binding revision workaround to AST2500 2026-01-09T13:33:37+00:00 Andrew Jeffery andrew@codeconstruct.com.au 2025-12-11T08:45:44+00:00 608c8030d32254917bee136234948f5f02221d0f Discovering a phandle to an AST2400 or AST2600 LPC node indicates an error for the purpose of the AST2500 pinctrl driver. Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org> 
Discovering a phandle to an AST2400 or AST2600 LPC node indicates an
error for the purpose of the AST2500 pinctrl driver.

Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
pinctrl: aspeed-g6: Add PCIe RC PERST pin group 2025-07-23T11:22:41+00:00 Jacky Chou jacky_chou@aspeedtech.com 2025-07-15T03:43:17+00:00 b1d4c90bffdeda6c0a304249358608e4ddb80377 The PCIe RC PERST uses SSPRST# as PERST# and enable this pin to output. Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/20250715034320.2553837-8-jacky_chou@aspeedtech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
The PCIe RC PERST uses SSPRST# as PERST#  and enable this pin
to output.

Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/20250715034320.2553837-8-jacky_chou@aspeedtech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: aspeed: Constify static 'pinctrl_desc' 2025-06-18T11:26:36+00:00 Krzysztof Kozlowski krzysztof.kozlowski@linaro.org 2025-06-11T06:13:37+00:00 e3d0571befa61a2692f6efb5f2c33926e99aea84 The local static 'struct pinctrl_desc' is not modified, so can be made const for code safety. Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20250611-pinctrl-const-desc-v2-5-b11c1d650384@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
The local static 'struct pinctrl_desc' is not modified, so can be made
const for code safety.

Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/20250611-pinctrl-const-desc-v2-5-b11c1d650384@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: aspeed-g6: Support drive-strength for GPIOF/G 2024-10-28T12:58:43+00:00 Billy Tsai billy_tsai@aspeedtech.com 2024-10-23T10:44:06+00:00 c34b20622e4f8da23503ca953b7aa23dc3c45659 Add drive strength configuration support for GPIO F and G groups. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://lore.kernel.org/20241023104406.4083460-1-billy_tsai@aspeedtech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add drive strength configuration support for GPIO F and G groups.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Link: https://lore.kernel.org/20241023104406.4083460-1-billy_tsai@aspeedtech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: aspeed-g6: Add NCSI pin group config 2024-06-26T10:41:07+00:00 Potin Lai potin.lai.pt@gmail.com 2024-06-21T09:31:42+00:00 f775c242307777d6c7739e21d2ef30987b737104 Based on the NCSI pin table (Table 181) in NCSI spec[1], the reference clock output pin (RMIIXRCLKO) is not needed on the management controller side. To optimize pin usage, add new NCSI pin group that excludes RMIIXRCLKO, reducing the number of required pins. LINK: [1] https://www.dmtf.org/sites/default/files/standards/documents/DSP0222_1.2.0a.pdf Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://lore.kernel.org/20240621093142.698529-3-potin.lai.pt@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Based on the NCSI pin table (Table 181) in NCSI spec[1], the reference
clock output pin (RMIIXRCLKO) is not needed on the management controller
side.

To optimize pin usage, add new NCSI pin group that excludes RMIIXRCLKO,
reducing the number of required pins.

LINK: [1] https://www.dmtf.org/sites/default/files/standards/documents/DSP0222_1.2.0a.pdf

Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Link: https://lore.kernel.org/20240621093142.698529-3-potin.lai.pt@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>