<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/pinctrl/Kconfig, branch v6.0</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>Merge tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2022-08-10T18:01:44+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2022-08-10T18:01:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=5e2e7383b57fa03ec2b00c82bb7f49a4a707c1f7'/>
<id>5e2e7383b57fa03ec2b00c82bb7f49a4a707c1f7</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "Outside the pinctrl driver and DT bindings we hit some Arm DT files,
  patched by the maintainers.

  Other than that it is business as usual.

  Core changes:

   - Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver).

  New drivers:

   - Intel Meteor Lake support.

   - Reneasas RZ/V2M and r8a779g0 (R-Car V4H).

   - AXP209 variants AXP221, AXP223 and AXP809.

   - Qualcomm MSM8909, PM8226, PMP8074 and SM6375.

   - Allwinner D1.

  Improvements:

   - Proper pin multiplexing in the AMD driver.

   - Mediatek MT8192 can use generic drive strength and pin bias, then
     fixes on top plus some I2C pin group fixes.

   - Have the Allwinner Sunplus SP7021 use the generic DT schema and
     make interrupts optional.

   - Handle Qualcomm SC7280 ADSP.

   - Handle Qualcomm MSM8916 CAMSS GP clock muxing.

   - High impedance bias on ZynqMP.

   - Serialize StarFive access to MMIO.

   - Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO"

* tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (117 commits)
  dt-bindings: pinctrl: qcom,pmic-gpio: add PM8226 constraints
  pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM
  pinctrl: qcom: sm8250: Fix PDC map
  pinctrl: amd: Fix an unused variable
  dt-bindings: pinctrl: mt8186: Add and use drive-strength-microamp
  dt-bindings: pinctrl: mt8186: Add gpio-line-names property
  ARM: dts: imxrt1170-pinfunc: Add pinctrl binding header
  pinctrl: amd: Use unicode for debugfs output
  pinctrl: amd: Fix newline declaration in debugfs output
  pinctrl: at91: Fix typo 'the the' in comment
  dt-bindings: pinctrl: st,stm32: Correct 'resets' property name
  pinctrl: mvebu: Missing a blank line after declarations.
  pinctrl: qcom: Add SM6375 TLMM driver
  dt-bindings: pinctrl: Add DT schema for SM6375 TLMM
  dt-bindings: pinctrl: mt8195: Use drive-strength-microamp in examples
  Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable"
  pinctrl: imx93: Add MODULE_DEVICE_TABLE()
  pinctrl: sunxi: Add driver for Allwinner D1
  pinctrl: sunxi: Make some layout parameters dynamic
  pinctrl: sunxi: Refactor register/offset calculation
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull pin control updates from Linus Walleij:
 "Outside the pinctrl driver and DT bindings we hit some Arm DT files,
  patched by the maintainers.

  Other than that it is business as usual.

  Core changes:

   - Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver).

  New drivers:

   - Intel Meteor Lake support.

   - Reneasas RZ/V2M and r8a779g0 (R-Car V4H).

   - AXP209 variants AXP221, AXP223 and AXP809.

   - Qualcomm MSM8909, PM8226, PMP8074 and SM6375.

   - Allwinner D1.

  Improvements:

   - Proper pin multiplexing in the AMD driver.

   - Mediatek MT8192 can use generic drive strength and pin bias, then
     fixes on top plus some I2C pin group fixes.

   - Have the Allwinner Sunplus SP7021 use the generic DT schema and
     make interrupts optional.

   - Handle Qualcomm SC7280 ADSP.

   - Handle Qualcomm MSM8916 CAMSS GP clock muxing.

   - High impedance bias on ZynqMP.

   - Serialize StarFive access to MMIO.

   - Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO"

* tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (117 commits)
  dt-bindings: pinctrl: qcom,pmic-gpio: add PM8226 constraints
  pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM
  pinctrl: qcom: sm8250: Fix PDC map
  pinctrl: amd: Fix an unused variable
  dt-bindings: pinctrl: mt8186: Add and use drive-strength-microamp
  dt-bindings: pinctrl: mt8186: Add gpio-line-names property
  ARM: dts: imxrt1170-pinfunc: Add pinctrl binding header
  pinctrl: amd: Use unicode for debugfs output
  pinctrl: amd: Fix newline declaration in debugfs output
  pinctrl: at91: Fix typo 'the the' in comment
  dt-bindings: pinctrl: st,stm32: Correct 'resets' property name
  pinctrl: mvebu: Missing a blank line after declarations.
  pinctrl: qcom: Add SM6375 TLMM driver
  dt-bindings: pinctrl: Add DT schema for SM6375 TLMM
  dt-bindings: pinctrl: mt8195: Use drive-strength-microamp in examples
  Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable"
  pinctrl: imx93: Add MODULE_DEVICE_TABLE()
  pinctrl: sunxi: Add driver for Allwinner D1
  pinctrl: sunxi: Make some layout parameters dynamic
  pinctrl: sunxi: Refactor register/offset calculation
  ...
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: Don't allow PINCTRL_AMD to be a module</title>
<updated>2022-07-18T10:47:28+00:00</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2022-07-13T17:59:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=41ef3c1a6bb0fd4a3f81170dd17de3adbff80783'/>
<id>41ef3c1a6bb0fd4a3f81170dd17de3adbff80783</id>
<content type='text'>
It was observed that by allowing pinctrl_amd to be loaded
later in the boot process that interrupts sent to the GPIO
controller early in the boot are not serviced.  The kernel treats
these as a spurious IRQ and disables the IRQ.

This problem was exacerbated because it happened on a system with
an encrypted partition so the kernel object was not accesssible for
an extended period of time while waiting for a passphrase.

To avoid this situation from occurring, stop allowing pinctrl-amd
from being built as a module and instead require it to be built-in
or disabled.

Reported-by: madcatx@atlas.cz
Suggested-by: jwrdegoede@fedoraproject.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216230
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Acked-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Link: https://lore.kernel.org/r/20220713175950.964-1-mario.limonciello@amd.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
It was observed that by allowing pinctrl_amd to be loaded
later in the boot process that interrupts sent to the GPIO
controller early in the boot are not serviced.  The kernel treats
these as a spurious IRQ and disables the IRQ.

This problem was exacerbated because it happened on a system with
an encrypted partition so the kernel object was not accesssible for
an extended period of time while waiting for a passphrase.

To avoid this situation from occurring, stop allowing pinctrl-amd
from being built as a module and instead require it to be built-in
or disabled.

Reported-by: madcatx@atlas.cz
Suggested-by: jwrdegoede@fedoraproject.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216230
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Acked-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Link: https://lore.kernel.org/r/20220713175950.964-1-mario.limonciello@amd.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: ocelot: allow building as a module</title>
<updated>2022-06-28T07:18:08+00:00</updated>
<author>
<name>Clément Léger</name>
<email>clement.leger@bootlin.com</email>
</author>
<published>2022-06-17T10:35:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=4425205ea38bef591a6c800bb47082fc35e788a0'/>
<id>4425205ea38bef591a6c800bb47082fc35e788a0</id>
<content type='text'>
Set PINCTRL_OCELOT config option as a tristate and add
MODULE_DEVICE_TABLE()/MODULE_LICENSE() to export appropriate
information. Moreover, switch from builtin_platform_driver()
to module_platform_driver().

Signed-off-by: Clément Léger &lt;clement.leger@bootlin.com&gt;
Link: https://lore.kernel.org/r/20220617103548.490092-1-clement.leger@bootlin.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Set PINCTRL_OCELOT config option as a tristate and add
MODULE_DEVICE_TABLE()/MODULE_LICENSE() to export appropriate
information. Moreover, switch from builtin_platform_driver()
to module_platform_driver().

Signed-off-by: Clément Léger &lt;clement.leger@bootlin.com&gt;
Link: https://lore.kernel.org/r/20220617103548.490092-1-clement.leger@bootlin.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: Add driver for Sunplus SP7021</title>
<updated>2022-01-30T01:55:41+00:00</updated>
<author>
<name>Wells Lu</name>
<email>wellslutw@gmail.com</email>
</author>
<published>2022-01-16T14:52:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=aa74c44be19c8b1de38d955c2c45c309991c805a'/>
<id>aa74c44be19c8b1de38d955c2c45c309991c805a</id>
<content type='text'>
Add driver for Sunplus SP7021 SoC.

Signed-off-by: Wells Lu &lt;wellslutw@gmail.com&gt;
Link: https://lore.kernel.org/r/1642344734-27229-3-git-send-email-wellslutw@gmail.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add driver for Sunplus SP7021 SoC.

Signed-off-by: Wells Lu &lt;wellslutw@gmail.com&gt;
Link: https://lore.kernel.org/r/1642344734-27229-3-git-send-email-wellslutw@gmail.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2022-01-12T18:56:08+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2022-01-12T18:56:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=e3084ed48fd6b661fe434da0cb36d7d6706cf27f'/>
<id>e3084ed48fd6b661fe434da0cb36d7d6706cf27f</id>
<content type='text'>
Pull pin control bulk updates from Linus Walleij:
 "Core changes:

   - New standard enumerator and corresponding device tree bindings for
     output impedance pin configuration. (Implemented and used in the
     Renesas rzg2l driver.)

   - Cleanup of Kconfig and Makefile to be somewhat orderly and
     alphabetic.

  New drivers:

   - Samsung Exynos 7885 pin controller.

   - Ocelot LAN966x pin controller.

   - Qualcomm SDX65 pin controller.

   - Qualcomm SM8450 pin controller.

   - Qualcomm PM8019, PM8226 and PM2250 pin controllers.

   - NXP/Freescale i.MXRT1050 pin controller.

   - Intel Thunder Bay pin controller.

  Enhancements:

   - Introduction of the string library helper function
     "kasprintf_strarray()" and subsequent use in Rockchip, ST and
     Armada pin control drivers, as well as the GPIO mockup driver.

   - The Ocelot pin controller has been extensively rewritten to use
     regmap and other modern kernel infrastructure.

   - The Microchip SGPIO driver has been converted to use regmap.

   - The SPEAr driver had been converted to use regmap.

   - Substantial cleanups and janitorial on the Apple pin control driver
     that was merged for v5.16.

   - Janitorial to remove of_node assignments in the GPIO portions that
     anyway get this handled in the GPIO core.

   - Minor cleanups and improvements in several pin controllers"

* tag 'pinctrl-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (98 commits)
  pinctrl: imx: fix assigning groups names
  dt-bindings: pinctrl: mt8195: add wrapping node of pin configurations
  pinctrl: bcm: ns: use generic groups &amp; functions helpers
  pinctrl: imx: fix allocation result check
  pinctrl: samsung: Use platform_get_irq_optional() to get the interrupt
  pinctrl: Propagate firmware node from a parent device
  dt-bindings: pinctrl: qcom: Add SDX65 pinctrl bindings
  pinctrl: add one more "const" for generic function groups
  pinctrl: keembay: rework loops looking for groups names
  pinctrl: keembay: comment process of building functions a bit
  pinctrl: imx: prepare for making "group_names" in "function_desc" const
  ARM: dts: gpio-ranges property is now required
  pinctrl: aspeed: fix unmet dependencies on MFD_SYSCON for PINCTRL_ASPEED
  pinctrl: Get rid of duplicate of_node assignment in the drivers
  pinctrl-sunxi: don't call pinctrl_gpio_direction()
  pinctrl-bcm2835: don't call pinctrl_gpio_direction()
  pinctrl: bcm2835: Silence uninit warning
  pinctrl: Sort Kconfig and Makefile entries alphabetically
  pinctrl: Add Intel Thunder Bay pinctrl driver
  dt-bindings: pinctrl: Add bindings for Intel Thunderbay pinctrl driver
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull pin control bulk updates from Linus Walleij:
 "Core changes:

   - New standard enumerator and corresponding device tree bindings for
     output impedance pin configuration. (Implemented and used in the
     Renesas rzg2l driver.)

   - Cleanup of Kconfig and Makefile to be somewhat orderly and
     alphabetic.

  New drivers:

   - Samsung Exynos 7885 pin controller.

   - Ocelot LAN966x pin controller.

   - Qualcomm SDX65 pin controller.

   - Qualcomm SM8450 pin controller.

   - Qualcomm PM8019, PM8226 and PM2250 pin controllers.

   - NXP/Freescale i.MXRT1050 pin controller.

   - Intel Thunder Bay pin controller.

  Enhancements:

   - Introduction of the string library helper function
     "kasprintf_strarray()" and subsequent use in Rockchip, ST and
     Armada pin control drivers, as well as the GPIO mockup driver.

   - The Ocelot pin controller has been extensively rewritten to use
     regmap and other modern kernel infrastructure.

   - The Microchip SGPIO driver has been converted to use regmap.

   - The SPEAr driver had been converted to use regmap.

   - Substantial cleanups and janitorial on the Apple pin control driver
     that was merged for v5.16.

   - Janitorial to remove of_node assignments in the GPIO portions that
     anyway get this handled in the GPIO core.

   - Minor cleanups and improvements in several pin controllers"

* tag 'pinctrl-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (98 commits)
  pinctrl: imx: fix assigning groups names
  dt-bindings: pinctrl: mt8195: add wrapping node of pin configurations
  pinctrl: bcm: ns: use generic groups &amp; functions helpers
  pinctrl: imx: fix allocation result check
  pinctrl: samsung: Use platform_get_irq_optional() to get the interrupt
  pinctrl: Propagate firmware node from a parent device
  dt-bindings: pinctrl: qcom: Add SDX65 pinctrl bindings
  pinctrl: add one more "const" for generic function groups
  pinctrl: keembay: rework loops looking for groups names
  pinctrl: keembay: comment process of building functions a bit
  pinctrl: imx: prepare for making "group_names" in "function_desc" const
  ARM: dts: gpio-ranges property is now required
  pinctrl: aspeed: fix unmet dependencies on MFD_SYSCON for PINCTRL_ASPEED
  pinctrl: Get rid of duplicate of_node assignment in the drivers
  pinctrl-sunxi: don't call pinctrl_gpio_direction()
  pinctrl-bcm2835: don't call pinctrl_gpio_direction()
  pinctrl: bcm2835: Silence uninit warning
  pinctrl: Sort Kconfig and Makefile entries alphabetically
  pinctrl: Add Intel Thunder Bay pinctrl driver
  dt-bindings: pinctrl: Add bindings for Intel Thunderbay pinctrl driver
  ...
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: starfive: Add pinctrl driver for StarFive SoCs</title>
<updated>2021-12-16T16:24:23+00:00</updated>
<author>
<name>Emil Renner Berthing</name>
<email>kernel@esmil.dk</email>
</author>
<published>2021-07-06T18:19:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=ec648f6b7686b716424e8e73eebb4c11ae199187'/>
<id>ec648f6b7686b716424e8e73eebb4c11ae199187</id>
<content type='text'>
Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which
is said to feature only minor changes to these pinctrl/GPIO parts.

For each "GPIO" there are two registers for configuring the output and
output enable signals which may come from other peripherals. Among these
are two special signals that are constant 0 and constant 1 respectively.
Controlling the GPIOs from software is done by choosing one of these
signals. In other words the same registers are used for both pin muxing
and controlling the GPIOs, which makes it easier to combine the pinctrl
and GPIO driver in one.

I wrote the pinconf and pinmux parts, but the GPIO part of the code is
based on the GPIO driver in the vendor tree written by Huan Feng with
cleanups and fixes by Drew and me.

Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
Reviewed-by: Andy Shevchenko &lt;andy.shevchenko@gmail.com&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Co-developed-by: Huan Feng &lt;huan.feng@starfivetech.com&gt;
Signed-off-by: Huan Feng &lt;huan.feng@starfivetech.com&gt;
Co-developed-by: Drew Fustini &lt;drew@beagleboard.org&gt;
Signed-off-by: Drew Fustini &lt;drew@beagleboard.org&gt;
Signed-off-by: Emil Renner Berthing &lt;kernel@esmil.dk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which
is said to feature only minor changes to these pinctrl/GPIO parts.

For each "GPIO" there are two registers for configuring the output and
output enable signals which may come from other peripherals. Among these
are two special signals that are constant 0 and constant 1 respectively.
Controlling the GPIOs from software is done by choosing one of these
signals. In other words the same registers are used for both pin muxing
and controlling the GPIOs, which makes it easier to combine the pinctrl
and GPIO driver in one.

I wrote the pinconf and pinmux parts, but the GPIO part of the code is
based on the GPIO driver in the vendor tree written by Huan Feng with
cleanups and fixes by Drew and me.

Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
Reviewed-by: Andy Shevchenko &lt;andy.shevchenko@gmail.com&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Co-developed-by: Huan Feng &lt;huan.feng@starfivetech.com&gt;
Signed-off-by: Huan Feng &lt;huan.feng@starfivetech.com&gt;
Co-developed-by: Drew Fustini &lt;drew@beagleboard.org&gt;
Signed-off-by: Drew Fustini &lt;drew@beagleboard.org&gt;
Signed-off-by: Emil Renner Berthing &lt;kernel@esmil.dk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: Sort Kconfig and Makefile entries alphabetically</title>
<updated>2021-12-09T13:49:39+00:00</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2021-12-09T11:34:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=b124c8bd50c7550ed966c09f69ffdbaaedc0aa15'/>
<id>b124c8bd50c7550ed966c09f69ffdbaaedc0aa15</id>
<content type='text'>
Sort Kconfig and Makefile entries alphabetically for better maintenance
in the future.

While at it fix some style issues, such as:
  - "Say Y"/"Say yes"/"Say Yes" --&gt; "Say Y"
  - "pullup/pulldown" --&gt; "pull-up and pull-down"
  - wrong indentation

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20211209113456.33977-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Sort Kconfig and Makefile entries alphabetically for better maintenance
in the future.

While at it fix some style issues, such as:
  - "Say Y"/"Say yes"/"Say Yes" --&gt; "Say Y"
  - "pullup/pulldown" --&gt; "pull-up and pull-down"
  - wrong indentation

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20211209113456.33977-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: Add Intel Thunder Bay pinctrl driver</title>
<updated>2021-12-09T02:17:39+00:00</updated>
<author>
<name>Lakshmi Sowjanya D</name>
<email>lakshmi.sowjanya.d@intel.com</email>
</author>
<published>2021-12-01T07:26:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=12422af8194df85243d68b11f8783de9d01e58dc'/>
<id>12422af8194df85243d68b11f8783de9d01e58dc</id>
<content type='text'>
About Intel Thunder Bay:
-----------------------
Intel Thunder Bay is a computer vision AI accelerator SoC based on ARM CPU.

Pinctrl IP:
----------
The SoC has a customised pinmux controller IP which controls pin
multiplexing and configuration.

Thunder Bay pinctrl IP is not based on and have nothing in common with the
existing pinctrl drivers. The registers used are incompatible with the
existing drivers, so it requires a new driver.

Add pinctrl driver to enable pin control support in the Intel Thunder Bay
SoC.

Co-developed-by: Kiran Kumar S &lt;kiran.kumar1.s@intel.com&gt;
Signed-off-by: Kiran Kumar S &lt;kiran.kumar1.s@intel.com&gt;
Signed-off-by: Lakshmi Sowjanya D &lt;lakshmi.sowjanya.d@intel.com&gt;
Link: https://lore.kernel.org/r/20211201072626.19599-3-lakshmi.sowjanya.d@intel.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
About Intel Thunder Bay:
-----------------------
Intel Thunder Bay is a computer vision AI accelerator SoC based on ARM CPU.

Pinctrl IP:
----------
The SoC has a customised pinmux controller IP which controls pin
multiplexing and configuration.

Thunder Bay pinctrl IP is not based on and have nothing in common with the
existing pinctrl drivers. The registers used are incompatible with the
existing drivers, so it requires a new driver.

Add pinctrl driver to enable pin control support in the Intel Thunder Bay
SoC.

Co-developed-by: Kiran Kumar S &lt;kiran.kumar1.s@intel.com&gt;
Signed-off-by: Kiran Kumar S &lt;kiran.kumar1.s@intel.com&gt;
Signed-off-by: Lakshmi Sowjanya D &lt;lakshmi.sowjanya.d@intel.com&gt;
Link: https://lore.kernel.org/r/20211201072626.19599-3-lakshmi.sowjanya.d@intel.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: add pinctrl/GPIO driver for Apple SoCs</title>
<updated>2021-10-26T22:16:52+00:00</updated>
<author>
<name>Joey Gouly</name>
<email>joey.gouly@arm.com</email>
</author>
<published>2021-10-26T17:58:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=a0f160ffcb83de6a04fa75f9e7bdfe969f2863f7'/>
<id>a0f160ffcb83de6a04fa75f9e7bdfe969f2863f7</id>
<content type='text'>
This driver adds support for the pinctrl / GPIO hardware found
on some Apple SoCs.

Co-developed-by: Stan Skowronek &lt;stan@corellium.com&gt;
Signed-off-by: Stan Skowronek &lt;stan@corellium.com&gt;
Signed-off-by: Joey Gouly &lt;joey.gouly@arm.com&gt;
Acked-by: Hector Martin &lt;marcan@marcan.st&gt;
Reviewed-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20211026175815.52703-5-joey.gouly@arm.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This driver adds support for the pinctrl / GPIO hardware found
on some Apple SoCs.

Co-developed-by: Stan Skowronek &lt;stan@corellium.com&gt;
Signed-off-by: Stan Skowronek &lt;stan@corellium.com&gt;
Signed-off-by: Joey Gouly &lt;joey.gouly@arm.com&gt;
Acked-by: Hector Martin &lt;marcan@marcan.st&gt;
Reviewed-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20211026175815.52703-5-joey.gouly@arm.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: Add Intel Keem Bay pinctrl driver</title>
<updated>2021-08-11T13:13:14+00:00</updated>
<author>
<name>Lakshmi Sowjanya D</name>
<email>lakshmi.sowjanya.d@intel.com</email>
</author>
<published>2021-08-06T14:25:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=ffd4e739358be036377563a0c6c33702c700e3ee'/>
<id>ffd4e739358be036377563a0c6c33702c700e3ee</id>
<content type='text'>
About Intel Keem Bay:
-------------------
Intel Keem Bay is a computer vision AI accelerator SoC based on ARM CPU.
Documentation of Keem Bay: Documentation/vpu/vpu-stack-overview.rst.

Pinctrl IP:
----------
The SoC has a customised pinmux controller IP which controls pin
multiplexing and configuration.

Keem Bay pinctrl IP is not based on and have nothing in common with the
existing pinctrl drivers. The registers used are incompatible with the
existing drivers, so it requires a new driver.

Add pinctrl driver to enable pin control support in the Intel Keem Bay SoC.

Co-developed-by: Vineetha G. Jaya Kumaran &lt;vineetha.g.jaya.kumaran@intel.com&gt;
Signed-off-by: Vineetha G. Jaya Kumaran &lt;vineetha.g.jaya.kumaran@intel.com&gt;
Co-developed-by: Vijayakannan Ayyathurai &lt;vijayakannan.ayyathurai@intel.com&gt;
Signed-off-by: Vijayakannan Ayyathurai &lt;vijayakannan.ayyathurai@intel.com&gt;
Signed-off-by: Lakshmi Sowjanya D &lt;lakshmi.sowjanya.d@intel.com&gt;
Reviewed-by: Mark Gross &lt;mgross@linux.intel.com&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Link: https://lore.kernel.org/r/20210806142527.29113-3-lakshmi.sowjanya.d@intel.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
About Intel Keem Bay:
-------------------
Intel Keem Bay is a computer vision AI accelerator SoC based on ARM CPU.
Documentation of Keem Bay: Documentation/vpu/vpu-stack-overview.rst.

Pinctrl IP:
----------
The SoC has a customised pinmux controller IP which controls pin
multiplexing and configuration.

Keem Bay pinctrl IP is not based on and have nothing in common with the
existing pinctrl drivers. The registers used are incompatible with the
existing drivers, so it requires a new driver.

Add pinctrl driver to enable pin control support in the Intel Keem Bay SoC.

Co-developed-by: Vineetha G. Jaya Kumaran &lt;vineetha.g.jaya.kumaran@intel.com&gt;
Signed-off-by: Vineetha G. Jaya Kumaran &lt;vineetha.g.jaya.kumaran@intel.com&gt;
Co-developed-by: Vijayakannan Ayyathurai &lt;vijayakannan.ayyathurai@intel.com&gt;
Signed-off-by: Vijayakannan Ayyathurai &lt;vijayakannan.ayyathurai@intel.com&gt;
Signed-off-by: Lakshmi Sowjanya D &lt;lakshmi.sowjanya.d@intel.com&gt;
Reviewed-by: Mark Gross &lt;mgross@linux.intel.com&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Link: https://lore.kernel.org/r/20210806142527.29113-3-lakshmi.sowjanya.d@intel.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
