linux.git/drivers/phy, branch v5.18-rc2

phy: PHY_FSL_LYNX_28G should depend on ARCH_LAYERSCAPE

2022-03-29T15:45:16+00:00

Freescale Layerscape Lynx 28G SerDes PHYs are only present on
Freescale/NXP Layerscape SoCs.

Move PHY_FSL_LYNX_28G outside the block for ARCH_MXC, as the latter
is meant for i.MX8 SoCs, which is a different family than Layerscape.
Add a dependency on ARCH_LAYERSCAPE, to prevent asking the user about
this driver when configuring a kernel without Layerscape SoC support.

Fixes: 02e2af20f4f9f2aa ("Merge tag 'char-misc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc")
Fixes: 8f73b37cf3fbda67 ("phy: add support for the Layerscape SerDes 28G")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Linus Torvalds

Merge tag 'char-misc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

2022-03-28T19:27:35+00:00

Pull char/misc and other driver updates from Greg KH:
 "Here is the big set of char/misc and other small driver subsystem
  updates for 5.18-rc1.

  Included in here are merges from driver subsystems which contain:

   - iio driver updates and new drivers

   - fsi driver updates

   - fpga driver updates

   - habanalabs driver updates and support for new hardware

   - soundwire driver updates and new drivers

   - phy driver updates and new drivers

   - coresight driver updates

   - icc driver updates

  Individual changes include:

   - mei driver updates

   - interconnect driver updates

   - new PECI driver subsystem added

   - vmci driver updates

   - lots of tiny misc/char driver updates

  All of these have been in linux-next for a while with no reported
  problems"

* tag 'char-misc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (556 commits)
  firmware: google: Properly state IOMEM dependency
  kgdbts: fix return value of __setup handler
  firmware: sysfb: fix platform-device leak in error path
  firmware: stratix10-svc: add missing callback parameter on RSU
  arm64: dts: qcom: add non-secure domain property to fastrpc nodes
  misc: fastrpc: Add dma handle implementation
  misc: fastrpc: Add fdlist implementation
  misc: fastrpc: Add helper function to get list and page
  misc: fastrpc: Add support to secure memory map
  dt-bindings: misc: add fastrpc domain vmid property
  misc: fastrpc: check before loading process to the DSP
  misc: fastrpc: add secure domain support
  dt-bindings: misc: add property to support non-secure DSP
  misc: fastrpc: Add support to get DSP capabilities
  misc: fastrpc: add support for FASTRPC_IOCTL_MEM_MAP/UNMAP
  misc: fastrpc: separate fastrpc device from channel context
  dt-bindings: nvmem: brcm,nvram: add basic NVMEM cells
  dt-bindings: nvmem: make "reg" property optional
  nvmem: brcm_nvram: parse NVRAM content into NVMEM cells
  nvmem: dt-bindings: Fix the error of dt-bindings check
  ...

phy: Remove duplicated include in phy-fsl-lynx-28g.c

2022-03-17T02:34:34+00:00

Fix following includecheck warning:
./drivers/phy/freescale/phy-fsl-lynx-28g.c: linux/workqueue.h is
included more than once.

Reported-by: Abaci Robot 
Signed-off-by: Yang Li 
Link: https://lore.kernel.org/r/20220315235603.59481-1-yang.lee@linux.alibaba.com
Signed-off-by: Jakub Kicinski

phy: add support for the Layerscape SerDes 28G

2022-03-14T10:41:50+00:00

This patch adds a new generic PHY driver to support the Lynx 28G SerDes
block found on some of the Layerscape SoCs such as LX2160A.
At the moment, only the following Ethernet protocols are supported:
SGMII/1000Base-X and 10GBaseR.

SerDes lanes which are not running an Ethernet protocol or a currently
supported Ethenet protocol will be left as it was configured through the
RCW (Reset Configuration Word) at boot time.

At probe time, the platform driver will read the current
configuration of both PLLs found on a SerDes block and will determine
what protocols are supported using that PLL.

For example, if a PLL is configured to generate a clock net (frate) of
5GHz the only protocols sustained by that PLL are SGMII/1000Base-X
(using a quarter of the full clock rate) and QSGMII using the full clock
net frequency on the lane.

On the .set_mode() callback, the PHY driver will first check if the
requested operating mode (protocol) is even supported by the current PLL
configuration and will error out if not.
Then, the lane is reconfigured to run on the requested protocol.

Signed-off-by: Ioana Ciornei 
Signed-off-by: David S. Miller

phy: qcom-qmp: add sc8280xp UFS PHY

2022-03-02T14:36:54+00:00

Reuse the SM8350 UFS PHY initialization sequence to add support for the
same found in the Qualcomm SC8280XP platform.

Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220225035105.2294599-2-bjorn.andersson@linaro.org
Signed-off-by: Vinod Koul

phy: qcom-snps: Add sc8280xp support

2022-03-02T14:36:54+00:00

The Qualcomm sc8280xp platform comes with a 5nm femto USB PHY which, in
contrast to previously seen platforms, has the SIDDQ bit in the COMMON0
register default to high.

So make the driver match on the 5nm compatible and make sure to clear
the SIDDQ bit on phy_init.

Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220225034049.2294207-2-bjorn.andersson@linaro.org
Signed-off-by: Vinod Koul

phy: cadence: Add Cadence D-PHY Rx driver

2022-03-02T14:24:42+00:00

The Cadence D-PHY can be configured in Tx (DSI) mode or Rx (CSI) mode.
Both modes have a different programming sequence and share little among
them. In addition, a PHY configured in Tx mode cannot be used in Rx mode
and vice versa. For this reason, create a separate driver for the Rx
mode to make it easier to read and maintain.

Signed-off-by: Pratyush Yadav 
Reviewed-by: Laurent Pinchart 

Link: https://lore.kernel.org/r/20220301111621.2992275-2-p.yadav@ti.com
Signed-off-by: Vinod Koul

phy: marvell: phy-mvebu-a3700-comphy: Add native kernel implementation

2022-02-25T13:42:21+00:00

Remove old RPC implementation and add a new native kernel implementation.

The old implementation uses ARM SMC API to issue RPC calls to ARM Trusted
Firmware which provides real implementation of PHY configuration.

But older versions of ARM Trusted Firmware do not provide this PHY
configuration functionality, simply returning: operation not supported; or
worse, some versions provide the configuration functionality incorrectly.

For example the firmware shipped in ESPRESSObin board has this older
version of ARM Trusted Firmware and therefore SATA, USB 3.0 and PCIe
functionality do not work with newer versions of Linux kernel.

Due to the above reasons, the following commits were introduced into Linux,
to workaround these issues by ignoring -EOPNOTSUPP error code from
phy-mvebu-a3700-comphy driver function phy_power_on():

commit 45aefe3d2251 ("ata: ahci: mvebu: Make SATA PHY optional for Armada
3720")
commit 3241929b67d2 ("usb: host: xhci: mvebu: make USB 3.0 PHY optional for
Armada 3720")
commit b0c6ae0f8948 ("PCI: aardvark: Fix initialization with old Marvell's
Arm Trusted Firmware")

Replace this RPC implementation with proper native kernel implementation,
which is independent on the firmware. Never return -EOPNOTSUPP for proper
arguments.

This should solve multiple issues with real-world boards, where it is not
possible or really inconvenient to change the firmware. Let's eliminate
these issues.

This implementation is ported directly from Armada 3720 comphy driver found
in newest version of ARM Trusted Firmware source code, but with various
fixes of register names, some added comments, some refactoring due to the
original code not conforming to kernel standards. Also PCIe mode poweroff
support was added here, and PHY reset support. These changes are also going
to be sent to ARM Trusted Firmware.

[ Pali did the porting from ATF.
  I (Marek) then fixed some register names, some various other things,
  added some comments and refactored the code to kernel standards. Also
  fixed PHY poweroff and added PHY reset. ]

Signed-off-by: Pali Rohár 
Acked-by: Miquel Raynal 
Signed-off-by: Marek Behún 
Link: https://lore.kernel.org/r/20220203214444.1508-3-kabel@kernel.org
Signed-off-by: Vinod Koul

phy: marvell: phy-mvebu-a3700-comphy: Remove port from driver configuration

2022-02-25T13:42:20+00:00

Port number is encoded into argument for SMC call. It is zero for SATA,
PCIe and also both USB 3.0 PHYs. It is non-zero only for Ethernet PHY
(incorrectly called SGMII) on lane 0. Ethernet PHY on lane 1 also uses zero
port number.

So construct "port" bits for SMC call argument can be constructed directly
from PHY type and lane number.

Change driver code to always pass zero port number for non-ethernet PHYs
and for ethernet PHYs determinate port number from lane number. This
simplifies the driver.

As port number from DT PHY configuration is not used anymore, remove whole
driver code which parses it. This also simplifies the driver.

Signed-off-by: Pali Rohár 
Signed-off-by: Marek Behún 
Reviewed-by: Miquel Raynal 
Link: https://lore.kernel.org/r/20220203214444.1508-2-kabel@kernel.org
Signed-off-by: Vinod Koul

phy: phy-brcm-usb: fixup BCM4908 support

2022-02-25T09:02:37+00:00

Just like every other family BCM4908 should get its own enum value. That
is required to properly handle it in chipset conditional code.

The real change is excluding BCM4908 from the PLL reprogramming code
(see brcmusb_usb3_pll_54mhz()). I'm not sure what's the BCM4908
reference clock frequency but:
1. BCM4908 custom driver from Broadcom's SDK doesn't reprogram PLL
2. Doing that in Linux driver stopped PHY handling some USB 3.0 devices

This change makes USB 3.0 PHY recognize e.g.:
1. 04e8:6860 - Samsung Electronics Co., Ltd Galaxy series, misc. (MTP mode)
2. 1058:259f - Western Digital My Passport 259F

Broadcom's STB SoCs come with a set of SUN_TOP_CTRL_* registers that
allow reading chip family and product ids. Such a block & register is
missing on BCM4908 so this commit introduces "compatible" string
specific binding.

Fixes: 4b402fa8e0b7 ("phy: phy-brcm-usb: support PHY on the BCM4908")
Signed-off-by: Rafał Miłecki 
Reviewed-by: Florian Fainelli 
Link: https://lore.kernel.org/r/20220218172459.10431-1-zajec5@gmail.com
Signed-off-by: Vinod Koul