linux.git/drivers/phy, branch v5.0-rc2

phy: fix build breakage: add PHY_MODE_SATA

2019-01-13T05:07:14+00:00

Commit 49e54187ae0b ("ata: libahci_platform: comply to PHY framework") uses
the PHY_MODE_SATA, but that enum had not yet been added. This caused a
build failure for me, with today's linux.git.

Also, there is a potentially conflicting (mis-named) PHY_MODE_SATA, hiding
in the Marvell Berlin SATA PHY driver.

Fix the build by:

    1) Renaming Marvell's defined value to a more scoped name,
       in order to avoid any potential conflicts: PHY_BERLIN_MODE_SATA.

    2) Adding the missing enum, which was going to be added anyway as part
       of [1].

[1] https://lkml.kernel.org/r/20190108163124.6409-3-miquel.raynal@bootlin.com

Fixes: 49e54187ae0b ("ata: libahci_platform: comply to PHY framework")

Signed-off-by: John Hubbard 
Acked-by: Jens Axboe 
Acked-by: Olof Johansson 
Cc: Grzegorz Jaszczyk 
Cc: Miquel Raynal 
Cc: Hans de Goede 
Signed-off-by: Linus Torvalds

phy: qcom-qmp: Expose provided clocks to DT

2018-12-12T04:32:12+00:00

Register a simple clock provider for the PHY pipe clock sources so that
device tree users can point at these clocks via phandles to the lane
nodes.

Signed-off-by: Evan Green 
Reviewed-by: Stephen Boyd 
Tested-by: Vivek Gautam 
Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qmp: Utilize fully-specified DT registers

2018-12-12T04:32:11+00:00

Utilize the newly fixed up DT bindings to get the tx2 and rx2 register
regions for the second lane of dual-lane PHYs. Before this change,
the driver was simply using lane one's register region and adding
0x400, which reached well beyond the DT-specified register
allocation. This would have been a crash were it not for the page size
on ARM64. Fix the driver not to rely on the magic of virtual memory by
using the newly specified DT register regions for tx2 and rx2.

In order to support existing device trees, this change also contains a
fallback mode for when those new register regions don't exist, which
reverts to the original behavior of overreaching and prints a complaint.

Signed-off-by: Evan Green 
Reviewed-by: Douglas Anderson 
Signed-off-by: Kishon Vijay Abraham I

phy: ti: fix semicolon.cocci warnings

2018-12-12T04:31:52+00:00

drivers/phy/ti/phy-gmii-sel.c:91:2-3: Unneeded semicolon

 Remove unneeded semicolon.

Generated by: scripts/coccinelle/misc/semicolon.cocci

Fixes: 1811851f4e73 ("phy: ti: introduce phy-gmii-sel driver")
CC: Grygorii Strashko 
Signed-off-by: kbuild test robot 
Signed-off-by: Kishon Vijay Abraham I

phy: dphy: Add configuration helpers

2018-12-12T04:31:51+00:00

The MIPI D-PHY spec defines default values and boundaries for most of the
parameters it defines. Introduce helpers to help drivers get meaningful
values based on their current parameters, and validate the boundaries of
these parameters if needed.

Signed-off-by: Maxime Ripard 
Signed-off-by: Kishon Vijay Abraham I

phy: Add configuration interface

2018-12-12T04:31:50+00:00

The phy framework is only allowing to configure the power state of the PHY
using the init and power_on hooks, and their power_off and exit
counterparts.

While it works for most, simple, PHYs supported so far, some more advanced
PHYs need some configuration depending on runtime parameters. These PHYs
have been supported by a number of means already, often by using ad-hoc
drivers in their consumer drivers.

That doesn't work too well however, when a consumer device needs to deal
with multiple PHYs, or when multiple consumers need to deal with the same
PHY (a DSI driver and a CSI driver for example).

So we'll add a new interface, through two funtions, phy_validate and
phy_configure. The first one will allow to check that a current
configuration, for a given mode, is applicable. It will also allow the PHY
driver to tune the settings given as parameters as it sees fit.

phy_configure will actually apply that configuration in the phy itself.

Signed-off-by: Maxime Ripard 
Signed-off-by: Kishon Vijay Abraham I

phy: add driver for Freescale i.MX8MQ USB3 PHY

2018-12-12T04:31:46+00:00

This is a cleaned up port of the downstream i.MX8MQ USB3 PHY driver.

Signed-off-by: Li Jun 
Signed-off-by: Lucas Stach 
Signed-off-by: Kishon Vijay Abraham I

phy: Use of_node_name_eq for node name comparisons

2018-12-12T04:31:44+00:00

Convert string compares of DT node names to use of_node_name_eq helper
instead. This removes direct access to the node name pointer.

For instances using of_node_cmp, this has the side effect of now using
case sensitive comparisons. This should not matter for any FDT based
system which all of these are.

Cc: Kishon Vijay Abraham I 
Cc: Heiko Stuebner 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: Rob Herring 
Signed-off-by: Kishon Vijay Abraham I

phy: ti: introduce phy-gmii-sel driver

2018-12-12T04:31:40+00:00

TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports two
10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII
interfaces. The interface mode is selected by configuring the MII mode
selection register(s) (GMII_SEL) in the System Control Module chapter
(SCM). GMII_SEL register(s) and bit fields placement in SCM are different
between SoCs while fields meaning is the same.

Historically CPSW external Port's interface mode selection configuration
was introduced using custom API and driver cpsw-phy-sel.c. This leads to
unnecessary driver, DT binding and custom API support effort.

This patch introduces CPSW Port's PHY Interface Mode selection Driver
(phy-gmii-sel) which implements standard Linux PHY interface and used
as a replacement for TI's specific driver cpsw-phy-sel.c and corresponding
custom API.

Cc: Kishon Vijay Abraham I 
Cc: Tony Lindgren 
Signed-off-by: Grygorii Strashko 
Signed-off-by: Kishon Vijay Abraham I

phy: mvebu-cp110-comphy: fix spelling in structure name

2018-12-12T04:31:39+00:00

Rename the mvebu_comhy_conf structure to be mvebu_comphy_conf, which is
probably what the original author meant.

Signed-off-by: Miquel Raynal 
Acked-by: Antoine Tenart 
Signed-off-by: Kishon Vijay Abraham I