linux.git/drivers/phy, branch v4.12

phy: qualcomm: phy-qcom-qmp: fix application of sizeof to pointer

2017-06-01T09:33:41+00:00

drivers/phy/qualcomm/phy-qcom-qmp.c:847:37-43: ERROR: application of sizeof to pointer

 sizeof when applied to a pointer typed expression gives the size of
 the pointer

Generated by: scripts/coccinelle/misc/noderef.cocci

CC: Vivek Gautam 
Signed-off-by: Fengguang Wu 
Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qmp: fix return value check in qcom_qmp_phy_create()

2017-05-19T08:43:39+00:00

In case of error, the function of_iomap() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should
be replaced with NULL test.

Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
Reviewed-by: Vivek Gautam 
Signed-off-by: Wei Yongjun 
Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qusb2: add NVMEM dependency

2017-04-10T11:13:41+00:00

With CONFIG_NVMEM=m and CONFIG_PHY_QCOM_QUSB2=y we get a link error from
calls to devm_nvmem_cell_get and nvmem_cell_read:

drivers/built-in.o: In function `qusb2_phy_probe':
binder.c:(.text+0x4750): undefined reference to `devm_nvmem_cell_get'
drivers/built-in.o: In function `qusb2_phy_init':
binder.c:(.text+0x489c): undefined reference to `nvmem_cell_read'

Fix this by adding a Kconfig dependency to ensure we can only have this
driver built in when the nvmem functions are also built in or we see the
empty stub functions. We can still build this driver as a module when the
nvmem core is build as module, too.

Fixes: deffad633413 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips")
Signed-off-by: Tobias Regnery 
Signed-off-by: Kishon Vijay Abraham I

phy: rockchip-usb: Add vbus regulator support.

2017-04-10T11:13:41+00:00

On rockchip devices vbus is supplied by a separate power supply, often
through a regulator. Add support for describing the the regulator in
device-tree following the same convention as several other usb phy's.

Signed-off-by: Sjoerd Simons 
Signed-off-by: Kishon Vijay Abraham I

phy: bcm-ns-usb3: split all writes into reg & val pairs

2017-04-10T11:13:41+00:00

So far all the PHY initialization was implemented using some totally
magic values. There was some pattern there but it wasn't clear what is
it about.

Thanks to the patch submitted by Broadcom:
[PATCH 5/6] phy: Add USB3 PHY support for Broadcom NSP SoC
and the upstream "iproc-mdio" driver we now know there is a MDIO bus
underneath with PHY(s) and their registers.

It allows us to clean the driver a bit by making all these values less
magical. The next step is switching to using a proper MDIO layer.

Signed-off-by: Rafał Miłecki 
Acked-by: Jon Mason 
Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2017-04-10T11:13:41+00:00

Qualcomm SOCs have QMP phy controller that provides support
to a number of controller, viz. PCIe, UFS, and USB.
Add a new driver, based on generic phy framework, for this
phy controller.

Signed-off-by: Vivek Gautam 
Tested-by: Srinivas Kandagatla 
Reviewed-by: Stephen Boyd 
Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips

2017-04-10T11:13:41+00:00

PHY transceiver driver for QUSB2 phy controller that provides
HighSpeed functionality for DWC3 controller present on
Qualcomm chipsets.

Signed-off-by: Vivek Gautam 
Reviewed-by: Stephen Boyd 
Signed-off-by: Kishon Vijay Abraham I

phy: rockchip-inno-usb2: add support of usb2-phy for rk3328

2017-04-10T11:13:41+00:00

Add usb2-phy config information in the data of match table for
rk3328.

Signed-off-by: Meng Dongyang 
Reviewed-by: Heiko Stuebner 
Signed-off-by: Kishon Vijay Abraham I

phy: phy-mt65xx-usb3: disable 100uA extraction from SS port to HS port

2017-04-10T11:13:40+00:00

There will be a problem if SS port is diasbled and HS port extracts
100uA from SS port, so disable extract 100uA from SS port in the case,
when disable it, PA0_RG_USB20_INTR_EN should be set, otherwise HS port
only works on LS.

Signed-off-by: Chunfeng Yun 
Signed-off-by: Kishon Vijay Abraham I

phy: phy-mt65xx-usb3: add support for new version phy

2017-04-10T11:13:40+00:00

There are some variations from mt2701 to mt2712:
1. banks shared by multiple ports are put back into each port,
    such as SPLLC and U2FREQ;
2. add a new bank MISC for u2port, and CHIP for u3port;
3. bank's offset in each port are also rearranged;

Signed-off-by: Chunfeng Yun 
Signed-off-by: Kishon Vijay Abraham I