linux.git/drivers/phy/qualcomm, branch v5.7-rc2

phy: qcom-qusb2: Add new overriding tuning parameters in QUSB2 V2 PHY

2020-03-20T14:04:29+00:00

Added support for overriding bias-ctrl-value,charge-ctrl-value and
hsdisc-trim-value params for QUSB2 V2 PHY

Signed-off-by: Sandeep Maheswaram 
Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qusb2: Add support for overriding tuning parameters in QUSB2 V2 PHY

2020-03-20T14:04:29+00:00

Added new structure for overriding tuning parameters in QUSB2 V2 PHY as the
override params are increased due to usage of generic QUSB2 V2 phy table.

Signed-off-by: Sandeep Maheswaram 
Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qusb2: Add generic QUSB2 V2 PHY support

2020-03-20T14:04:29+00:00

Add generic QUSB2 V2 PHY table so the respective phys
can use the same table.

Signed-off-by: Sandeep Maheswaram 
Reviewed-by: Matthias Kaehlcke 
Reviewed-by: Stephen Boyd 
Signed-off-by: Kishon Vijay Abraham I

phy: qualcomm: usb: Add SuperSpeed PHY driver

2020-03-20T14:04:29+00:00

Controls Qualcomm's SS PHY 1.0.0 implemented on various SoCs on both the
20nm and 28nm process nodes.

Based on Sriharsha Allenki's  original code.

[bod: Removed dependency on extcon.
      Switched to gpio-usb-conn to handle VBUS On/Off
      Switched to usb-role-switch to bind gpio-usb-conn to DWC3]
Signed-off-by: Jorge Ramirez-Ortiz 
Cc: Jorge Ramirez-Ortiz 
Cc: Sriharsha Allenki's 
Cc: Andy Gross 
Cc: Bjorn Andersson 
Cc: Kishon Vijay Abraham I 
Cc: Philipp Zabel 
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Philipp Zabel 
Tested-by: Bjorn Andersson 
Signed-off-by: Bryan O'Donoghue 
Signed-off-by: Kishon Vijay Abraham I

phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver

2020-03-20T14:04:29+00:00

Adds Qualcomm 28nm Hi-Speed USB PHY driver support. This PHY is usually
paired with Synopsys DWC3 USB controllers on Qualcomm SoCs.

The PHY can come in two flavours femtoPHY or picoPHY. This commit adds
support for the femtoPHY with the possibility of extending to the picoPHY
with additional future commits. Both PHYs are on a 28 nanometer process
node.

[bod: Updated qcom_snps_hsphy_set_mode to match new method signature
      Added disjunct on mode > 0
      Removed regulator_set_voltage() in favour of setting floor in dts
      Removed 'snps' and from driver name
      Extended commit log to mention femtoPHY and picoPHY for future
      reference.]

Signed-off-by: Shawn Guo 
Cc: Andy Gross 
Cc: Bjorn Andersson 
Cc: Kishon Vijay Abraham I 
Cc: Philipp Zabel 
Cc: Jorge Ramirez-Ortiz 
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Tested-by: Bjorn Andersson 
Signed-off-by: Bryan O'Donoghue 
Signed-off-by: Kishon Vijay Abraham I

phy: qcom: qmp: Use power_on/off ops for PCIe

2020-03-20T14:04:29+00:00

The PCIe PHY initialization requires the attached device to be present,
which is primarily achieved by the PCI controller driver.  So move the
logic from init/exit to power_on/power_off.

Signed-off-by: Bjorn Andersson 
Reviewed-by: John Stultz 
Reviewed-by: Vinod Koul 
Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qmp: Add MSM8996 UFS QMP support

2020-03-20T14:04:29+00:00

The support for the 14nm MSM8996 UFS PHY is currently handled by the
UFS-specific 14nm QMP driver, due to the earlier need for additional
operations beyond the standard PHY API.

Add support for this PHY to the common QMP driver, to allow us to remove
the old driver.

Acked-by: Rob Herring 
Reviewed-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Signed-off-by: Kishon Vijay Abraham I

phy: qcom: qmp: Add SDM845 QHP PCIe PHY

2020-02-21T08:36:14+00:00

Add the GEN3 QHP PCIe PHY found in SDM845.

Tested-by: Julien Massot 
Tested-by: Vinod Koul 
Reviewed-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Signed-off-by: Kishon Vijay Abraham I

phy: qcom: qmp: Add SDM845 PCIe QMP PHY support

2020-02-21T08:36:14+00:00

qcom_qmp_phy_init() is extended to support the additional register
writes needed in PCS MISC and the appropriate sequences and resources
are defined for the GEN2 PCIe QMP PHY found in SDM845.

Tested-by: Vinod Koul 
Reviewed-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Signed-off-by: Kishon Vijay Abraham I

Merge tag 'phy-for-5.6_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next

2020-01-17T06:52:26+00:00

Kishon writes:

phy: for 5.6

*) Add support in PHY core to create link between PHY consumer and PHY
   provider
*) Add DisplayPort PHY configuration set to be used for negotiating the
   configurations to be used between DisplayPort controller and
   DisplayPort PHY
*) Add PHY wrapper driver (configure inputs to Cadence Sierra PHY) for
   TI's J721E SoC and adapt Cadence Sierra PHY driver to be used for
   J721E SoC (Supports USB and PCIe)
*) Add PHY driver for eMMC PHY in Intel LGM SoC
*) Add PHY support for 7216 and 7211 Broadcom SoCs which uses the new
   Synopsys USB Controller
*) Add support for 16nm SATA PHY present in Broadcom 7216 SoC
*) Fix lost packet issue, fix MDIO from getting inaccessible, fix
   occasional transaction failures, fix USB driver from crashing in
   Broadcom USB PHY driver
*) Fix missing PCS SW reset in UFS PHY of Qualcomm SM8150
*) Use "struct phy_configure_opts_mipi_dphy" to pass parameters from
   display controller to rockchip-inno-dsidphy
*) Other cleanups including compile testing for some of the PHY drivers,
   fixing Kconfig indentation, duplicate writes in drivers etc.,

Signed-off-by: Kishon Vijay Abraham I 

* tag 'phy-for-5.6_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (54 commits)
  dt-bindings: phy: Add PHY_TYPE_DP definition
  phy: ti: j721e-wiz: Fix return value check in wiz_probe()
  dt-bindings: usb: Convert Allwinner A80 USB PHY controller to a schema
  phy: intel-lgm-emmc: Fix warning by adding missing MODULE_LICENSE
  phy: ti: j721e-wiz: Manage typec-gpio-dir
  dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO
  phy: cadence: Sierra: add phy_reset hook
  phy: cadence: Sierra: remove redundant initialization of pointer regmap
  phy: Add DisplayPort configuration options
  phy: Enable compile testing for some of drivers
  phy: mediatek: Fix Kconfig indentation
  phy: intel-lgm-emmc: Add support for eMMC PHY
  dt-bindings: phy: intel-emmc-phy: Add YAML schema for LGM eMMC PHY
  phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC
  dt-bindings: phy: Document WIZ (SERDES wrapper) bindings
  phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove()
  phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz
  phy: cadence: Sierra: Change MAX_LANES of Sierra to 16
  phy: cadence: Sierra: Check for PLL lock during PHY power on
  phy: cadence: Sierra: Get reset control "array" for each link
  ...