linux.git/drivers/pci, branch v2.6.29 Linux kernel source tree PCIe: portdrv: call pci_disable_device during remove 2009-03-12T19:42:35+00:00 Alex Chiang achiang@hp.com 2009-03-08T02:35:47+00:00 d89987193631bf23d1735c55d13a06d4b8d0e9bd The PCIe port driver calls pci_enable_device() during probe but never calls pci_disable_device() during remove. Cc: stable@kernel.org Signed-off-by: Alex Chiang <achiang@hp.com> Signed-off-by: Matthew Wilcox <willy@linux.intel.com> 
The PCIe port driver calls pci_enable_device() during probe but
never calls pci_disable_device() during remove.

Cc: stable@kernel.org
Signed-off-by: Alex Chiang <achiang@hp.com>
Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
pci: Fix typo in message while disabling HT MSI mapping 2009-03-12T19:42:29+00:00 Prakash Punnoor prakash@punnoor.de 2009-03-06T09:10:35+00:00 6a958d5b28e4a180458e0d319d2e4bb5c4b7da3e "Enabling" should read "Disabling" Signed-off-by: Prakash Punnoor <prakash@punnoor.de> Signed-off-by: Matthew Wilcox <willy@linux.intel.com> 
"Enabling" should read "Disabling"

Signed-off-by: Prakash Punnoor <prakash@punnoor.de>
Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
pci: don't disable too many HT MSI mapping 2009-03-12T19:41:57+00:00 Prakash Punnoor prakash@punnoor.de 2009-03-05T23:45:12+00:00 7726c3308a92b4a4c3bd059059498fca0e6f8e48 Prakash's system needs MSI disabled on some bridges, but not all. This seems to be the minimal fix for 2.6.29, but should be replaced during 2.6.30. Signed-off-by: Prakash Punnoor <prakash@punnoor.de> Signed-off-by: Matthew Wilcox <willy@linux.intel.com> 
Prakash's system needs MSI disabled on some bridges, but not all.
This seems to be the minimal fix for 2.6.29, but should be replaced
during 2.6.30.

Signed-off-by: Prakash Punnoor <prakash@punnoor.de>
Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
powerpc/pseries: The RPA PCI hotplug driver depends on EEH 2009-03-12T19:10:02+00:00 Michael Ellerman michael@ellerman.id.au 2009-03-06T03:39:14+00:00 3f3b902ed8147c42a4a9764014c758e6b3f42f51 The RPA PCI hotplug driver calls EEH routines, so should depend on EEH. Also PPC_PSERIES implies PPC64, so remove that. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Matthew Wilcox <willy@linux.intel.com> 
The RPA PCI hotplug driver calls EEH routines, so should depend on
EEH. Also PPC_PSERIES implies PPC64, so remove that.

Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
PCIe: AER: during disable, check subordinate before walking 2009-03-12T19:09:51+00:00 Alex Chiang achiang@hp.com 2009-03-06T02:28:40+00:00 cb4cb4ac7338c28b047760be187355ed9c783e72 Commit 47a8b0cc (Enable PCIe AER only after checking firmware support) wants to walk the PCI bus in the remove path to disable AER, and calls pci_walk_bus for downstream bridges. Unfortunately, in the remove path, we remove devices and bridges in a depth-first manner, starting with the furthest downstream bridge and working our way backwards. The furthest downstream bridges will not have a dev->subordinate, and we hit a NULL deref in pci_walk_bus. Check for dev->subordinate first before attempting to walk the PCI hierarchy below us. Acked-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Alex Chiang <achiang@hp.com> Signed-off-by: Matthew Wilcox <willy@linux.intel.com> 
Commit 47a8b0cc (Enable PCIe AER only after checking firmware
support) wants to walk the PCI bus in the remove path to disable
AER, and calls pci_walk_bus for downstream bridges.

Unfortunately, in the remove path, we remove devices and bridges
in a depth-first manner, starting with the furthest downstream
bridge and working our way backwards.

The furthest downstream bridges will not have a dev->subordinate,
and we hit a NULL deref in pci_walk_bus.

Check for dev->subordinate first before attempting to walk the
PCI hierarchy below us.

Acked-by: Andrew Patterson <andrew.patterson@hp.com>
Signed-off-by: Alex Chiang <achiang@hp.com>
Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
PCI: Add PCI quirk to disable L0s ASPM state for 82575 and 82598 2009-03-12T19:09:41+00:00 Alexander Duyck alexander.h.duyck@intel.com 2009-03-05T18:57:28+00:00 649426efcfbc67a8b033497151816cbac9fd0cfa This patch is intended to disable L0s ASPM link state for 82598 (ixgbe) parts due to the fact that it is possible to corrupt TX data when coming back out of L0s on some systems. The workaround had been added for 82575 (igb) previously, but did not use the ASPM api. This quirk uses the ASPM api to prevent the ASPM subsystem from re-enabling the L0s state. Instead of adding the fix in igb to the ixgbe driver as well it was decided to move it into a pci quirk. It is necessary to move the fix out of the driver and into a pci quirk in order to prevent the issue from occuring prior to driver load to handle the possibility of the device being passed to a VM via direct assignment. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> CC: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Matthew Wilcox <willy@linux.intel.com> 
This patch is intended to disable L0s ASPM link state for 82598 (ixgbe)
parts due to the fact that it is possible to corrupt TX data when coming
back out of L0s on some systems.  The workaround had been added for 82575
(igb) previously, but did not use the ASPM api.  This quirk uses the ASPM
api to prevent the ASPM subsystem from re-enabling the L0s state.

Instead of adding the fix in igb to the ixgbe driver as well it was
decided to move it into a pci quirk.  It is necessary to move the fix out
of the driver and into a pci quirk in order to prevent the issue from
occuring prior to driver load to handle the possibility of the device being
passed to a VM via direct assignment.

Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
CC: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6 2009-02-26T22:43:42+00:00 Linus Torvalds torvalds@linux-foundation.org 2009-02-26T22:43:42+00:00 4bdc1b96504f5f562b129afd48ca03d79aeb1fd9 * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: PCI: AMD 813x B2 devices do not need boot interrupt quirk PCI: Enable PCIe AER only after checking firmware support PCI: pciehp: Handle interrupts that happen during initialization. PCI: don't enable too many HT MSI mappings PCI: add some sysfs ABI docs PCI quirk: enable MSI on 8132 
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:
  PCI: AMD 813x B2 devices do not need boot interrupt quirk
  PCI: Enable PCIe AER only after checking firmware support
  PCI: pciehp: Handle interrupts that happen during initialization.
  PCI: don't enable too many HT MSI mappings
  PCI: add some sysfs ABI docs
  PCI quirk: enable MSI on 8132
PCI: AMD 813x B2 devices do not need boot interrupt quirk 2009-02-26T22:08:09+00:00 Stefan Assmann sassmann@novell.com 2009-02-26T18:46:48+00:00 bbe194433baeadc953f49e3795b41ffffc5486dd Turns out that the new AMD 813x devices do not need the quirk_disable_amd_813x_boot_interrupt quirk to be run on them. If it is, no interrupts are seen on the PCI-X adapter. From: Stefan Assmann <sassmann@novell.com> Reported-by: Jamie Wellnitz <Jamie.Wellnitz@emulex.com> Tested-by: Jamie Wellnitz <Jamie.Wellnitz@emulex.com> Cc: stable <stable@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Jesse Barnes <jbarnes@hobbes.lan> 
Turns out that the new AMD 813x devices do not need the
quirk_disable_amd_813x_boot_interrupt quirk to be run on them.  If it
is, no interrupts are seen on the PCI-X adapter.

From: Stefan Assmann <sassmann@novell.com>
Reported-by: Jamie Wellnitz <Jamie.Wellnitz@emulex.com>
Tested-by: Jamie Wellnitz <Jamie.Wellnitz@emulex.com>
Cc: stable <stable@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: Jesse Barnes <jbarnes@hobbes.lan>
Merge git://git.infradead.org/iommu-2.6 2009-02-25T17:31:21+00:00 Linus Torvalds torvalds@linux-foundation.org 2009-02-25T17:31:21+00:00 60042600c57be5737cd9d6869e7144f7fe786274 * git://git.infradead.org/iommu-2.6: intel-iommu: fix endless "Unknown DMAR structure type" loop VT-d: handle Invalidation Queue Error to avoid system hang intel-iommu: fix build error with INTR_REMAP=y and DMAR=n 
* git://git.infradead.org/iommu-2.6:
  intel-iommu: fix endless "Unknown DMAR structure type" loop
  VT-d: handle Invalidation Queue Error to avoid system hang
  intel-iommu: fix build error with INTR_REMAP=y and DMAR=n
PCI: Enable PCIe AER only after checking firmware support 2009-02-24T17:47:46+00:00 Andrew Patterson andrew.patterson@hp.com 2009-02-20T23:04:59+00:00 1f9f13c8d59c1d8da1a602b71d1ab96d1d37d69e The PCIe port driver currently sets the PCIe AER error reporting bits for any root or switch port without first checking to see if firmware will grant control. This patch moves setting these bits to the AER service driver aer_enable_port routine. The bits are then set for the root port and any downstream switch ports after the check for firmware support (aer_osc_setup) is made. The patch also unsets the bits in a similar fashion when the AER service driver is unloaded. Reviewed-by: Alex Chiang <achiang@hp.com> Signed-off-by: Andrew Patterson <andrew.patterson@hp.com> Signed-off-by: Jesse Barnes <jbarnes@hobbes.lan> 
The PCIe port driver currently sets the PCIe AER error reporting bits for
any root or switch port without first checking to see if firmware will grant
control. This patch moves setting these bits to the AER service driver
aer_enable_port routine.  The bits are then set for the root port and any
downstream switch ports after the check for firmware support (aer_osc_setup)
is made. The patch also unsets the bits in a similar fashion when the AER
service driver is unloaded.

Reviewed-by: Alex Chiang <achiang@hp.com>
Signed-off-by: Andrew Patterson <andrew.patterson@hp.com>
Signed-off-by: Jesse Barnes <jbarnes@hobbes.lan>