linux.git/drivers/pci, branch v2.6.13

Ignore disabled ROM resources at setup

2005-08-26T17:49:22+00:00

Writing even a disabled value seems to mess up some matrox graphics
cards.  It may be a card-related issue, but we may also be writing
reserved low bits in the result.

This was a fall-out of switching x86 over to the generic PCI resource
allocation code, and needs more debugging.  In particular, the old x86
code defaulted to not doing any resource allocations at all for ROM
resources.

In the meantime, this has been reported to make X happier by Helge
Hafting .

Signed-off-by: Linus Torvalds

Only pre-allocate 256 bytes of cardbio IO range

2005-08-26T17:40:10+00:00

It may seem small, but most cards need much less, if any, and this not
only makes the code adhere to the comment, it seems to fix a boot-time
lockup on a ThinkPad 380XD laptop reported by Tero Roponen 

Signed-off-by: Linus Torvalds

[PATCH] PCI Hotplug: new contact info

2005-08-17T04:06:24+00:00

Signed-off-by: Kristen Carlson Accardi 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Linus Torvalds

[PATCH] PCI: fix quirk-6700-fix.patch

2005-08-17T04:06:24+00:00

drivers/built-in.o(.text+0x32c3): In function `quirk_pcie_pxh':
/usr/src/25/drivers/pci/quirks.c:1312: undefined reference to `disable_msi_mode'

Signed-off-by: Andrew Morton 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Linus Torvalds

[PATCH] PCI: 6700/6702PXH quirk

2005-08-17T04:06:24+00:00

On the 6700/6702 PXH part, a MSI may get corrupted if an ACPI hotplug
driver and SHPC driver in MSI mode are used together.

This patch will prevent MSI from being enabled for the SHPC as part of
an early pci quirk, as well as on any pci device which sets the no_msi
bit.

Signed-off-by: Kristen Carlson Accardi 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Linus Torvalds

Revert "[PATCH] PCI: restore BAR values..."

2005-08-09T01:46:09+00:00

Revert commit fec59a711eef002d4ef9eb8de09dd0a26986eb77, which is
breaking sparc64 that doesn't have a working pci_update_resource.

We'll re-do this after 2.6.13 when we'll do it all properly.

[PATCH] VIA VT8235 PCI quirk

2005-08-08T18:46:24+00:00

Like many other southbridges from different manufacturers, VIA VT8235
chip has two non-standard BARs for power management and SMBus registers
(see the datasheet at http://www.via.com.tw).

This new quirk routine fixes boot problem with 2.6.13-rc2/rc6 kernels on
Targa Visionary 811 Athlon64 laptop, as reported by Mikael Pettersson
.

Signed-off-by: Ivan Kokshaysky 
Signed-off-by: Linus Torvalds

[PATCH] Fix restore of 64-bit PCI BAR's

2005-08-07T16:50:56+00:00

For 64-bit BAR[i] only pci_dev->resource[i] is valid, ->resource[i+1]
slot is unused and contains zeroes in all fields.

So when we update a PCI BAR, all we need is just to check that we're
going to update a _valid_ resource.

Also make sure to write high bits - use "x >> 16 >> 16" (rather than the
simpler ">> 32") to avoid warnings on 32-bit architectures where we're
not going to have any high bits.

Signed-off-by: Linus Torvalds

[PATCH] PCI: restore BAR values after D3hot->D0 for devices that need it

2005-08-05T04:32:46+00:00

Some PCI devices (e.g. 3c905B, 3c556B) lose all configuration
(including BARs) when transitioning from D3hot->D0.  This leaves such
a device in an inaccessible state.  The patch below causes the BARs
to be restored when enabling such a device, so that its driver will
be able to access it.

The patch also adds pci_restore_bars as a new global symbol, and adds a
correpsonding EXPORT_SYMBOL_GPL for that.

Some firmware (e.g. Thinkpad T21) leaves devices in D3hot after a
(re)boot.  Most drivers call pci_enable_device very early, so devices
left in D3hot that lose configuration during the D3hot->D0 transition
will be inaccessible to their drivers.

Drivers could be modified to account for this, but it would
be difficult to know which drivers need modification.  This is
especially true since often many devices are covered by the same
driver.  It likely would be necessary to replicate code across dozens
of drivers.

The patch below should trigger only when transitioning from D3hot->D0
(or at boot), and only for devices that have the "no soft reset" bit
cleared in the PM control register.  I believe it is safe to include
this patch as part of the PCI infrastructure.

The cleanest implementation of pci_restore_bars was to call
pci_update_resource.  Unfortunately, that does not currently exist
for the sparc64 architecture.  The patch below includes a null
implemenation of pci_update_resource for sparc64.

Some have expressed interest in making general use of the the
pci_restore_bars function, so that has been exported to GPL licensed
modules.

Signed-off-by: John W. Linville 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Linus Torvalds

pci: make bus resource start address override minimum IO address

2005-08-02T21:55:40+00:00

The reason we have PCIBIOS_MIN_IO and PCIBIOS_MIN_CARDBUS_IO is because
we want to protect badly documented motherboard PCI resources and thus
don't want to allocate new resources in low IO/MEM space.

However, if we have already discovered a PCI bridge with a specified
resource base, that should override that decision.

This change will allow us to move the "careful" region upwards without
resulting in problems allocating resources in low mappings.  This was
brought on by us having allocated a bus resource at 0x1000, conflicting
with a undocumented VAIO Sony PI resources.