linux.git/drivers/net/phy, branch v5.7-rc2

net: marvell10g: soft-reset the PHY when coming out of low power

2020-04-14T23:48:09+00:00

Soft-reset the PHY when coming out of low power mode, which seems to
be necessary with firmware versions 0.3.3.0 and 0.3.10.0.

This depends on ("net: marvell10g: report firmware version")

Fixes: c9cc1c815d36 ("net: phy: marvell10g: place in powersave mode at probe")
Reported-by: Matteo Croce 
Tested-by: Matteo Croce 
Reviewed-by: Andrew Lunn 
Signed-off-by: Russell King 
Reviewed-by: Florian Fainelli 
Signed-off-by: David S. Miller

net: marvell10g: report firmware version

2020-04-14T23:48:09+00:00

Report the firmware version when probing the PHY to allow issues
attributable to firmware to be diagnosed.

Tested-by: Matteo Croce 
Signed-off-by: Russell King 
Reviewed-by: Andrew Lunn 
Reviewed-by: Florian Fainelli 
Signed-off-by: David S. Miller

net: phy: micrel: use genphy_read_status for KSZ9131

2020-04-14T23:25:30+00:00

KSZ9131 will not work with some switches due to workaround for KSZ9031
introduced in commit d2fd719bcb0e83cb39cfee22ee800f98a56eceb3
("net/phy: micrel: Add workaround for bad autoneg").
Use genphy_read_status instead of dedicated ksz9031_read_status.

Fixes: bff5b4b37372 ("net: phy: micrel: add Microchip KSZ9131 initial driver")
Signed-off-by: Atsushi Nemoto 
Signed-off-by: David S. Miller

net: phy: marvell: Fix pause frame negotiation

2020-04-11T23:51:09+00:00

The negotiation of flow control / pause frame modes was broken since
commit fcf1f59afc67 ("net: phy: marvell: rearrange to use
genphy_read_lpa()") moved the setting of phydev->duplex below the
phy_resolve_aneg_pause call. Due to a check of DUPLEX_FULL in that
function, phydev->pause was no longer set.

Fix it by moving the parsing of the status variable before the blocks
dealing with the pause frames.

As the Marvell 88E1510 datasheet does not specify the timing between the
link status and the "Speed and Duplex Resolved" bit, we have to force
the link down as long as the resolved bit is not set, to avoid reporting
link up before we even have valid Speed/Duplex.

Tested with a Marvell 88E1510 (RGMII to Copper/1000Base-T)

Fixes: fcf1f59afc67 ("net: phy: marvell: rearrange to use genphy_read_lpa()")
Signed-off-by: Clemens Gruber 
Signed-off-by: Jakub Kicinski

Documentation: mdio_bus.c - fix warnings

2020-04-08T01:33:48+00:00

Fix wrong parameter description and related warnings at 'make htmldocs'.

Signed-off-by: Lothar Rubusch 
Reviewed-by: Florian Fainelli 
Acked-by: Randy Dunlap 
Tested-by: Randy Dunlap 
Signed-off-by: David S. Miller

net: phy: micrel: kszphy_resume(): add delay after genphy_resume() before accessing PHY registers

2020-04-03T23:04:24+00:00

After the power-down bit is cleared, the chip internally triggers a
global reset. According to the KSZ9031 documentation, we have to wait at
least 1ms for the reset to finish.

If the chip is accessed during reset, read will return 0xffff, while
write will be ignored. Depending on the system performance and MDIO bus
speed, we may or may not run in to this issue.

This bug was discovered on an iMX6QP system with KSZ9031 PHY and
attached PHY interrupt line. If IRQ was used, the link status update was
lost. In polling mode, the link status update was always correct.

The investigation showed, that during a read-modify-write access, the
read returned 0xffff (while the chip was still in reset) and
corresponding write hit the chip _after_ reset and triggered (due to the
0xffff) another reset in an undocumented bit (register 0x1f, bit 1),
resulting in the next write being lost due to the new reset cycle.

This patch fixes the issue by adding a 1...2 ms sleep after the
genphy_resume().

Fixes: 836384d2501d ("net: phy: micrel: Add specific suspend")
Signed-off-by: Oleksij Rempel 
Reviewed-by: Andrew Lunn 
Reviewed-by: Florian Fainelli 
Signed-off-by: David S. Miller

net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035

2020-04-01T18:20:47+00:00

The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set
for the values that comprise the fields, not zero-bits-set.

This patch fixes the clock frequency configuration for ATH8030 and
ATH8035 Atheros PHYs by removing the erroneous "~".

To reproduce this bug, configure the PHY  with the device tree binding
"qca,clk-out-frequency" and remove the machine specific PHY fixups.

Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding")
Signed-off-by: Oleksij Rempel 
Reported-by: Russell King 
Reviewed-by: Russell King 
Tested-by: Russell King 
Signed-off-by: David S. Miller

net: phylink: add separate pcs operations structure

2020-03-30T18:52:27+00:00

Add a separate set of PCS operations, which MAC drivers can use to
couple phylink with their associated MAC PCS layer.  The PCS
operations include:

- pcs_get_state() - reads the link up/down, resolved speed, duplex
   and pause from the PCS.
- pcs_config() - configures the PCS for the specified mode, PHY
   interface type, and setting the advertisement.
- pcs_an_restart() - restarts 802.3 in-band negotiation with the
   link partner
- pcs_link_up() - informs the PCS that link has come up, and the
   parameters of the link. Link parameters are used to program the
   PCS for fixed speed and non-inband modes.

Reviewed-by: Andrew Lunn 
Reviewed-by: Florian Fainelli 
Signed-off-by: Russell King 
Signed-off-by: David S. Miller

net: phylink: rename 'ops' to 'mac_ops'

2020-03-30T18:52:27+00:00

Rename the bland 'ops' member of struct phylink to be a more
descriptive 'mac_ops' - this is necessary as we're about to introduce
another set of operations.

Reviewed-by: Andrew Lunn 
Reviewed-by: Florian Fainelli 
Signed-off-by: Russell King 
Signed-off-by: David S. Miller

net: phylink: change phylink_mii_c22_pcs_set_advertisement() prototype

2020-03-30T18:52:27+00:00

Change phylink_mii_c22_pcs_set_advertisement() to take only the PHY
interface and advertisement mask, rather than the full phylink state.

Reviewed-by: Andrew Lunn 
Reviewed-by: Florian Fainelli 
Signed-off-by: Russell King 
Signed-off-by: David S. Miller