linux.git/drivers/net/phy/realtek.c, branch v6.7

net: phy: realtek: Disable clock on suspend

2023-06-07T08:52:24+00:00

For PHYs that call rtl821x_probe() where an external clock can be
configured, make sure that the clock is disabled
when ->suspend() is called and enabled on resume.

The PHY_ALWAYS_CALL_SUSPEND is added to ensure that the suspend function
is actually always called.

Reviewed-by: Florian Fainelli 
Signed-off-by: Detlev Casanova 
Signed-off-by: David S. Miller

net: phy: realtek: Add optional external PHY clock

2023-06-07T08:52:24+00:00

In some cases, the PHY can use an external clock source instead of a
crystal.

Add an optional clock in the phy node to make sure that the clock source
is enabled, if specified, before probing.

Reviewed-by: Florian Fainelli 
Reviewed-by: Andrew Lunn 
Signed-off-by: Detlev Casanova 
Signed-off-by: David S. Miller

net: phy: realtek: add support for RTL8211F(D)(I)-VD-CG

2022-08-22T11:47:18+00:00

RTL8211F(D)(I)-VD-CG is the pin-to-pin upgrade chip from
RTL8211F(D)(I)-CG.

Add new PHY ID for this chip.
It does not support RTL8211F_PHYCR2 anymore, so remove the w/r operation
of this register.

Signed-off-by: Clark Wang 
Signed-off-by: Wei Fang 
Signed-off-by: David S. Miller

net: phy: realtek: add support for RTL8365MB-VC internal PHYs

2021-10-18T13:02:56+00:00

The RTL8365MB-VC ethernet switch controller has 4 internal PHYs for its
user-facing ports. All that is needed is to let the PHY driver core
pick up the IRQ made available by the switch driver.

Signed-off-by: Alvin Šipraga 
Reviewed-by: Florian Fainelli 
Reviewed-by: Linus Walleij 
Signed-off-by: David S. Miller

net: phy: realtek: net: Fix less than zero comparison of a u16

2021-06-09T22:32:08+00:00

The comparisons of the u16 values priv->phycr1 and priv->phycr2 to less
than zero always false because they are unsigned. Fix this by using an
int for the assignment and less than zero check.

Addresses-Coverity: ("Unsigned compared against 0")
Fixes: 0a4355c2b7f8 ("net: phy: realtek: add dt property to disable CLKOUT clock")
Fixes: d90db36a9e74 ("net: phy: realtek: add dt property to enable ALDPS mode")
Signed-off-by: Colin Ian King 
Signed-off-by: David S. Miller

net: phy: realtek: add delay to fix RXC generation issue

2021-06-08T18:41:24+00:00

PHY will delay about 11.5ms to generate RXC clock when switching from
power down to normal operation. Read/write registers would also cause RXC
become unstable and stop for a while during this process. Realtek engineer
suggests 15ms or more delay can workaround this issue.

Signed-off-by: Joakim Zhang 
Signed-off-by: David S. Miller

net: phy: realtek: add dt property to enable ALDPS mode

2021-06-08T18:41:24+00:00

If enable Advance Link Down Power Saving (ALDPS) mode, it will change
crystal/clock behavior, which cause RXC clock stop for dozens to hundreds
of miliseconds. This is comfirmed by Realtek engineer. For some MACs, it
needs RXC clock to support RX logic, after this patch, PHY can generate
continuous RXC clock during auto-negotiation.

ALDPS default is disabled after hardware reset, it's more reasonable to
add a property to enable this feature, since ALDPS would introduce side effect.
This patch adds dt property "realtek,aldps-enable" to enable ALDPS mode
per users' requirement.

Jisheng Zhang enables this feature, changes the default behavior. Since
mine patch breaks the rule that new implementation should not break
existing design, so Cc'ed let him know to see if it can be accepted.

Cc: Jisheng Zhang 
Signed-off-by: Joakim Zhang 
Signed-off-by: David S. Miller

net: phy: realtek: add dt property to disable CLKOUT clock

2021-06-08T18:41:23+00:00

CLKOUT is enabled by default after PHY hardware reset, this patch adds
"realtek,clkout-disable" property for user to disable CLKOUT clock
to save PHY power.

Per RTL8211F guide, a PHY reset should be issued after setting these
bits in PHYCR2 register. After this patch, CLKOUT clock output to be
disabled.

Signed-off-by: Joakim Zhang 
Signed-off-by: David S. Miller

net: phy: realtek: Add support for RTL9000AA/AN

2021-01-23T02:06:42+00:00

RTL9000AA/AN as 100BASE-T1 is following:
- 100 Mbps
- Full duplex
- Link Status Change Interrupt
- Master/Slave configuration

Signed-off-by: Yuusuke Ashizuka 
Signed-off-by: Torii Kenichi 
Reviewed-by: Andrew Lunn 
Link: https://lore.kernel.org/r/20210121080254.21286-1-ashiduka@fujitsu.com
Signed-off-by: Jakub Kicinski

net: phy: realtek: read actual speed on rtl8211f to detect downshift

2020-11-25T20:29:40+00:00

The rtl8211f supports downshift and before commit 5502b218e001
("net: phy: use phy_resolve_aneg_linkmode in genphy_read_status")
the read-back of register MII_CTRL1000 was used to detect the
negotiated link speed.
The code added in commit d445dff2df60 ("net: phy: realtek: read
actual speed to detect downshift") is working fine also for this
phy and it's trivial re-using it to restore the downshift
detection on rtl8211f.

Add the phy specific read_status() pointing to the existing
function rtlgen_read_status().

Signed-off-by: Antonio Borneo 
Link: https://lore.kernel.org/r/478f871a-583d-01f1-9cc5-2eea56d8c2a7@huawei.com
Tested-by: Yonglong Liu 
Link: https://lore.kernel.org/r/20201124230756.887925-1-antonio.borneo@st.com
Signed-off-by: Jakub Kicinski