linux.git/drivers/net/can/flexcan.c, branch v5.8

can: flexcan: poll MCR_LPM_ACK instead of GPR ACK for stop mode acknowledgment

2019-12-08T11:21:35+00:00

Stop Mode is entered when Stop Mode is requested at chip level and
MCR[LPM_ACK] is asserted by the FlexCAN.

Double check with IP owner, the MCR[LPM_ACK] bit should be polled for
stop mode acknowledgment, not the acknowledgment from chip level which
is used to gate flexcan clocks.

This patch depends on:

    b7603d080ffc ("can: flexcan: add low power enter/exit acknowledgment helper")

Fixes: 5f186c257fa4 (can: flexcan: fix stop mode acknowledgment)
Tested-by: Sean Nyekjaer 
Signed-off-by: Joakim Zhang 
Cc: linux-stable  # >= v5.0
Signed-off-by: Marc Kleine-Budde

can: flexcan: add low power enter/exit acknowledgment helper

2019-12-08T10:52:02+00:00

The MCR[LPMACK] read-only bit indicates that FlexCAN is in a lower-power
mode (Disabled mode, Doze mode, Stop mode).

The CPU can poll this bit to know when FlexCAN has actually entered low
power mode. The low power enter/exit acknowledgment helper will reduce
code duplication for disabled mode, doze mode and stop mode.

Tested-by: Sean Nyekjaer 
Signed-off-by: Joakim Zhang 
Signed-off-by: Marc Kleine-Budde

can: flexcan: fix possible deadlock and out-of-order reception after wakeup

2019-12-08T10:52:02+00:00

When suspending, and there is still CAN traffic on the interfaces the
flexcan immediately wakes the platform again. As it should :-). But it
throws this error msg:

[ 3169.378661] PM: noirq suspend of devices failed

On the way down to suspend the interface that throws the error message
calls flexcan_suspend() but fails to call flexcan_noirq_suspend(). That
means flexcan_enter_stop_mode() is called, but on the way out of suspend
the driver only calls flexcan_resume() and skips flexcan_noirq_resume(),
thus it doesn't call flexcan_exit_stop_mode(). This leaves the flexcan
in stop mode, and with the current driver it can't recover from this
even with a soft reboot, it requires a hard reboot.

This patch fixes the deadlock when using self wakeup, by calling
flexcan_exit_stop_mode() from flexcan_resume() instead of
flexcan_noirq_resume().

This also fixes another issue: CAN frames are received out-of-order in
first IRQ handler run after wakeup.

The problem is that the wakeup latency from frame reception to the IRQ
handler (where the CAN frames are sorted by timestamp) is much bigger
than the time stamp counter wrap around time. This means it's
impossible to sort the CAN frames by timestamp.

The reason is that the controller exits stop mode during noirq resume,
which means it receives frames immediately, but interrupt handling is
still not possible.

So exit stop mode during resume stage instead of noirq resume fixes this
issue.

Fixes: de3578c198c6 ("can: flexcan: add self wakeup support")
Signed-off-by: Sean Nyekjaer 
Tested-by: Sean Nyekjaer 
Signed-off-by: Joakim Zhang 
Cc: linux-stable  # >= v5.0
Signed-off-by: Marc Kleine-Budde

can: flexcan: flexcan_mailbox_read() make use of flexcan_write64() to mark the mailbox as read

2019-11-11T20:58:12+00:00

In the previous patch the function flexcan_write64() was introduced.

This patch replaces the open coded variant in flexcan_mailbox_read()
that marks a mailbox as read, by a single call to flexcan_write64().

Signed-off-by: Marc Kleine-Budde

can: flexcan: flexcan_irq(): add support for TX mailbox in iflag1

2019-11-11T20:58:12+00:00

The flexcan IP core has up to 64 mailboxes, each one has a corresponding
interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
imask1 or imask2 registers.

The driver will always use the last mailbox for TX, which falls into the iflag2
register.

To support CANFD the payload size has to increase to 64 bytes and the number of
mailboxes will decrease so much that the TX mailbox will be handled in the
iflag1 register.

This patch add support to handle the TX mailbox independent whether it's
in iflag1 or iflag2 by introducing th flexcan_read_reg_iflag_tx()
function, similar to flexcan_read_reg_iflag_rx(), for the read path.

For the write path the function flexcan_write64() is added.

Signed-off-by: Marc Kleine-Budde

can: flexcan: flexcan_read_reg_iflag_rx(): optimize reading

2019-11-11T20:58:11+00:00

The flexcan IP core has up to 64 mailboxes, each one has a corresponding
interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
imask1 or imask2 registers.

In the timestamp (i.e. non FIFO) mode the driver needs to mask all non RX
interrupt sources, it uses the precomputed value rx_mask of struct flexcan_priv
for this.

In certain use cases, for example the CANFD mode, the contents of the iflag2
register is completely masked.

This patch optimizes the flexcan_read_reg_iflag_rx() function by not reading
the iflag1 or iflag2 register if the contents is masked.

Signed-off-by: Marc Kleine-Budde

can: flexcan: introduce struct flexcan_priv::tx_mask and make use of it

2019-11-11T20:58:11+00:00

The current driver uses FLEXCAN_IFLAG2_MB() to generate the mask to check for
the TX complete interrupt. This works well, as the driver will always use the
last mailbox for TX, which falls into the iflag2 register.

To support CANFD the payload size has to increase to 64 bytes and the
number of mailboxes will decrease so much that the TX mailbox will be
handled in the iflag1 register.

This patch introduces a tx_mask in the struct flexcan_priv (similar to rx_mask)
and makes use of it. The actual support to handle the TX mailbox in iflag1 will
be added in the next patches.

Signed-off-by: Marc Kleine-Budde

can: flexcan: convert struct flexcan_priv::rx_mask{1,2} to rx_mask

2019-11-11T20:58:11+00:00

The flexcan IP core has up to 64 mailboxes, each one has a corresponding
interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
imask1 or imask2 registers.

In the timestamp (i.e. non FIFO) mode the driver needs to mask out all non RX
interrupt sources and uses the precomputed values rx_mask1 and rx_mask2 of
struct flexcan_priv for this.

This patch merges the two u32 rx_mask1 and rx_mask2 to a single u64 rx_mask
variable, which simplifies the code a bit.

Signed-off-by: Marc Kleine-Budde

can: flexcan: remove TX mailbox bit from struct flexcan_priv::rx_mask{1,2}

2019-11-11T20:58:11+00:00

The flexcan IP core has up to 64 mailboxes, each one has a corresponding
interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
imask1 or imask2 registers.

In the timestamp (i.e. non FIFO) mode the driver needs to mask out all
non RX interrupt sources and uses the precomputed values rx_mask1 and
rx_mask2 of struct flexcan_priv for this.

Currently these values cannot be used directly, as they contain the TX
mailbox flag. This patch removes the TX flag from flexcan_priv::rx_mask1
and flexcan_priv::rx_mask2, and sets the TX flag directly when writing
the regs->iflag1 and regs->iflag2 into the hardware.

Signed-off-by: Marc Kleine-Budde

can: flexcan: rename struct flexcan_priv::reg_imask{1,2}_default to rx_mask{1,2}

2019-11-11T20:58:11+00:00

The flexcan IP core has up to 64 mailboxes, each one has a corresponding
interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
imask1 or imask2 registers.

In the timestamp (i.e. non FIFO) mode the driver needs to mask out all
non RX interrupt sources and uses the precomputed values
reg_imask1_default and reg_imask2_default of struct flexcan_priv for
this.

However in the current driver the reg_imask{1,2}_default cannot be used
directly to get the pending RX interrupts. The TX interrupt is part of
these variables, so it needs to be masked out, too.

This is a preparation patch to clean up calculation of the pending RX
interrupts, it only renames the variables from

    reg_imask{1,2}_default

to

    rx_mask{1,2}

To better reflect their meaning after the complete conversion. This
change is done with the following sed command:

    sed -i -e "s/reg_imask\(1\|2\)_default/rx_mask\1/" drivers/net/can/flexcan.c

Signed-off-by: Marc Kleine-Budde