linux.git/drivers/mmc/host/Makefile, branch v5.5 Linux kernel source tree mmc: Add Actions Semi Owl SoCs SD/MMC driver 2019-11-13T15:10:16+00:00 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org 2019-09-16T15:45:44+00:00 ff65ffe46d2839b434dbab77dd3af0cb4f6d2a98 Add SD/MMC driver for Actions Semi Owl SoCs. This driver currently supports standard, high speed, SDR12, SDR25 and SDR50. DDR50 mode is supported but it is untested. There is no SDIO support for now. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 
Add SD/MMC driver for Actions Semi Owl SoCs. This driver currently
supports standard, high speed, SDR12, SDR25 and SDR50. DDR50 mode is
supported but it is untested. There is no SDIO support for now.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
mmc: sdhci-milbeaut: add Milbeaut SD controller driver 2019-11-13T15:10:16+00:00 Takao Orito orito.takao@socionext.com 2019-09-10T01:41:06+00:00 dd79b7e367033bacff8ff8c1bd85b2a848cf475d SD Host controller on Milbeaut consists of two controller parts. One is core controller F_SDH30, this is similar to sdhci-fujitsu controller. Another is bridge controller. This bridge controller is not compatible with sdhci-fujitsu controller. This is special for Milbeaut series. This has some functions. For example, reset control, clock enable/select for SDR50/25/12, set property of SD physical pins, retuning control, set capabilityies. This bridge controller requires special procedures at reset or clock enablement or change for further tuning of clock. Signed-off-by: Takao Orito <orito.takao@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 
SD Host controller on Milbeaut consists of two controller parts.
One is core controller F_SDH30, this is similar to sdhci-fujitsu
controller.
Another is bridge controller.
This bridge controller is not compatible with sdhci-fujitsu controller.
This is special for Milbeaut series. This has some functions.
For example, reset control, clock enable/select for SDR50/25/12, set
property of SD physical pins, retuning control, set capabilityies.

This bridge controller requires special procedures at reset or clock
enablement or change for further tuning of clock.

Signed-off-by: Takao Orito <orito.takao@socionext.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
mmc: host: sdhci-pci: Add Genesys Logic GL975x support 2019-09-27T18:48:20+00:00 Ben Chuang ben.chuang@genesyslogic.com.tw 2019-09-11T07:23:44+00:00 e51df6ce668a8f75ce27f83ce0f60103c568c375 Add support for the GL9750 and GL9755 chipsets. Enable v4 mode and wait 5ms after set 1.8V signal enable for GL9750/ GL9755. Fix the value of SDHCI_MAX_CURRENT register and use the vendor tuning flow for GL9750. Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 
Add support for the GL9750 and GL9755 chipsets.

Enable v4 mode and wait 5ms after set 1.8V signal enable for GL9750/
GL9755. Fix the value of SDHCI_MAX_CURRENT register and use the vendor
tuning flow for GL9750.

Co-developed-by: Michael K Johnson <johnsonm@danlj.org>
Signed-off-by: Michael K Johnson <johnsonm@danlj.org>
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
mmc: sdhci-of-aspeed: Add support for the ASPEED SD controller 2019-09-11T13:58:39+00:00 Andrew Jeffery andrew@aj.id.au 2019-08-07T00:36:29+00:00 bb7b8ec62dfb9b255027c3a54d01f12fc3bd1d2c Add a minimal driver for ASPEED's SD controller, which exposes two SDHCIs. The ASPEED design implements a common register set for the SDHCIs, and moves some of the standard configuration elements out to this common area (e.g. 8-bit mode, and card detect configuration which is not currently supported). The SD controller has a dedicated hardware interrupt that is shared between the slots. The common register set exposes information on which slot triggered the interrupt; early revisions of the patch introduced an irqchip for the register, but reality is it doesn't behave as an irqchip, and the result fits awkwardly into the irqchip APIs. Instead I've taken the simple approach of using the IRQ as a shared IRQ with some minor performance impact for the second slot. Ryan was the original author of the patch - I've taken his work and massaged it to drop the irqchip support and rework the devicetree integration. The driver has been smoke tested under qemu against a minimal SD controller model and lightly tested on an ast2500-evb. Signed-off-by: Ryan Chen <ryanchen.aspeed@gmail.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 
Add a minimal driver for ASPEED's SD controller, which exposes two
SDHCIs.

The ASPEED design implements a common register set for the SDHCIs, and
moves some of the standard configuration elements out to this common
area (e.g. 8-bit mode, and card detect configuration which is not
currently supported).

The SD controller has a dedicated hardware interrupt that is shared
between the slots. The common register set exposes information on which
slot triggered the interrupt; early revisions of the patch introduced an
irqchip for the register, but reality is it doesn't behave as an
irqchip, and the result fits awkwardly into the irqchip APIs. Instead
I've taken the simple approach of using the IRQ as a shared IRQ with
some minor performance impact for the second slot.

Ryan was the original author of the patch - I've taken his work and
massaged it to drop the irqchip support and rework the devicetree
integration. The driver has been smoke tested under qemu against a
minimal SD controller model and lightly tested on an ast2500-evb.

Signed-off-by: Ryan Chen <ryanchen.aspeed@gmail.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
mmc: sdhci_am654: Add Initial Support for AM654 SDHCI driver 2018-12-17T07:26:24+00:00 Faiz Abbas faiz_abbas@ti.com 2018-12-10T18:35:07+00:00 41fd4caeb00bbd6dc55f056f3e8e956697b0760d The host controllers on TI's AM654 SOCs are not compatible with the phy and consumer model of the sdhci-of-arasan driver. It turns out that for optimal operation at higher speeds, a special tuning procedure needs to be implemented which involves configuration of platform specific phy registers. Therefore, branch out to a new sdhci_am654 driver and add the phy register space with all phy configurations to it. Populate AM654 specific callbacks to sdhci_ops and add SDHCI_QUIRKS wherever applicable. Only add support for upto High Speed for SD card and upto DDR52 speed mode for eMMC. Higher speeds will be added in subsequent patches. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 
The host controllers on TI's AM654 SOCs are not compatible with
the phy and consumer model of the sdhci-of-arasan driver. It turns out
that for optimal operation at higher speeds, a special tuning procedure
needs to be implemented which involves configuration of platform
specific phy registers.

Therefore, branch out to a new sdhci_am654 driver and add the phy
register space with all phy configurations to it. Populate AM654
specific callbacks to sdhci_ops and add SDHCI_QUIRKS wherever
applicable.

Only add support for upto High Speed for SD card and upto DDR52 speed
mode for eMMC. Higher speeds will be added in subsequent patches.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
mmc: add new Alcor Micro Cardreader SD/MMC driver 2018-12-17T07:26:24+00:00 Oleksij Rempel linux@rempel-privat.de 2018-12-02T10:30:46+00:00 c5413ad815a675b5c98a002353d8e96b44b164e9 This driver provides support for Alcor Micro AU6601 and AU6621 SD/MMC controller. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 
This driver provides support for Alcor Micro AU6601 and AU6621
SD/MMC controller.

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
mmc: mmci: add stm32 sdmmc variant 2018-10-09T07:16:53+00:00 Ludovic Barre ludovic.barre@st.com 2018-10-08T12:08:55+00:00 46b723dd867d599420fb640c0eaf2a866ef721d4 This patch adds a stm32 sdmmc variant, rev 1.1. Introduces a new Manufacturer id "0x53, ascii 'S' to define new stm32 sdmmc family with clean range of amba revision/configurations bits (corresponding to sdmmc_ver register with major/minor fields). Add 2 variants properties: -dma_lli, to enable link list support. -stm32_idmabsize_mask, defines the range of SDMMC_IDMABSIZER register which specify the number bytes per buffer. DT properties for sdmmc: -Indicate signal directions (only one property for d0dir, d123dir, cmd_dir) -Select command and data phase relation. -Select "clock in" from an external driver. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 
This patch adds a stm32 sdmmc variant, rev 1.1.
Introduces a new Manufacturer id "0x53, ascii 'S' to define
new stm32 sdmmc family with clean range of amba
revision/configurations bits (corresponding to sdmmc_ver
register with major/minor fields).
Add 2 variants properties:
-dma_lli, to enable link list support.
-stm32_idmabsize_mask, defines the range of SDMMC_IDMABSIZER register
 which specify the number bytes per buffer.

DT properties for sdmmc:
-Indicate signal directions (only one property
 for d0dir, d123dir, cmd_dir)
-Select command and data phase relation.
-Select "clock in" from an external driver.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
mmc: sdhci-sprd: Add Spreadtrum's initial host controller 2018-10-08T09:40:43+00:00 Chunyan Zhang chunyan.zhang@unisoc.com 2018-08-30T08:21:44+00:00 fb8bd90f83c4dd86bc7fdae406152d63c5852f92 This patch adds the initial support of Secure Digital Host Controller Interface compliant controller found in some latest Spreadtrum chipsets. This patch has been tested on the version of SPRD-R11 controller. R11 is a variant based on SD v4.0 specification. With this driver, R11 mmc can be initialized, can be mounted, read and written. Original-by: Billows Wu <billows.wu@unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 
This patch adds the initial support of Secure Digital Host Controller
Interface compliant controller found in some latest Spreadtrum chipsets.
This patch has been tested on the version of SPRD-R11 controller.

R11 is a variant based on SD v4.0 specification.

With this driver, R11 mmc can be initialized, can be mounted, read and
written.

Original-by: Billows Wu <billows.wu@unisoc.com>
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
mmc: uniphier-sd: add UniPhier SD/eMMC controller driver 2018-10-08T09:40:43+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2018-08-23T04:44:18+00:00 3fd784f745dd1747863775a99ec749619ee6759c Here is another TMIO MMC variant found in Socionext UniPhier SoCs. As commit b6147490e6aa ("mmc: tmio: split core functionality, DMA and MFD glue") said, these MMC controllers use the IP from Panasonic. However, the MMC controller in the TMIO (Toshiba Mobile IO) MFD chip was the first upstreamed user of this IP. The common driver code for this IP is now called 'tmio-mmc-core' in Linux although it is a historical misnomer. Anyway, this driver select's MMC_TMIO_CORE to borrow the common code from tmio-mmc-core.c Older UniPhier SoCs (LD4, Pro4, sLD8) support the external DMA engine like renesas_sdhi_sys_dmac.c. The difference is UniPhier SoCs use a single DMA channel whereas Renesas chips request separate channels for RX and TX. Newer UniPhier SoCs (Pro5 and later) support the internal DMA engine like renesas_sdhi_internal_dmac.c The register map is almost the same, so I guess Renesas and Socionext use the same internal DMA hardware. The main difference is, the register offsets are doubled for Renesas. Renesas Socionext SDHI UniPhier DM_CM_DTRAN_MODE 0x820 0x410 DM_CM_DTRAN_CTRL 0x828 0x414 DM_CM_RST 0x830 0x418 DM_CM_INFO1 0x840 0x420 DM_CM_INFO1_MASK 0x848 0x424 DM_CM_INFO2 0x850 0x428 DM_CM_INFO2_MASK 0x858 0x42c DM_DTRAN_ADDR 0x880 0x440 DM_DTRAN_ADDREX --- 0x444 This comes from the difference of host->bus_shift; 2 for Renesas SoCs, and 1 for UniPhier SoCs. Also, the datasheet for UniPhier SoCs defines DM_DTRAN_ADDR and DM_DTRAN_ADDREX as two separate registers. It could be possible to factor out the DMA common code by introducing some hooks to cope with platform quirks, but this patch does not touch that for now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 
Here is another TMIO MMC variant found in Socionext UniPhier SoCs.

As commit b6147490e6aa ("mmc: tmio: split core functionality, DMA and
MFD glue") said, these MMC controllers use the IP from Panasonic.

However, the MMC controller in the TMIO (Toshiba Mobile IO) MFD chip
was the first upstreamed user of this IP.  The common driver code
for this IP is now called 'tmio-mmc-core' in Linux although it is a
historical misnomer.

Anyway, this driver select's MMC_TMIO_CORE to borrow the common code
from tmio-mmc-core.c

Older UniPhier SoCs (LD4, Pro4, sLD8) support the external DMA engine
like renesas_sdhi_sys_dmac.c.  The difference is UniPhier SoCs use a
single DMA channel whereas Renesas chips request separate channels for
RX and TX.

Newer UniPhier SoCs (Pro5 and later) support the internal DMA engine
like renesas_sdhi_internal_dmac.c  The register map is almost the same,
so I guess Renesas and Socionext use the same internal DMA hardware.
The main difference is, the register offsets are doubled for Renesas.

                        Renesas      Socionext
                        SDHI         UniPhier
  DM_CM_DTRAN_MODE      0x820        0x410
  DM_CM_DTRAN_CTRL      0x828        0x414
  DM_CM_RST             0x830        0x418
  DM_CM_INFO1           0x840        0x420
  DM_CM_INFO1_MASK      0x848        0x424
  DM_CM_INFO2           0x850        0x428
  DM_CM_INFO2_MASK      0x858        0x42c
  DM_DTRAN_ADDR         0x880        0x440
  DM_DTRAN_ADDREX        ---         0x444

This comes from the difference of host->bus_shift; 2 for Renesas SoCs,
and 1 for UniPhier SoCs.  Also, the datasheet for UniPhier SoCs defines
DM_DTRAN_ADDR and DM_DTRAN_ADDREX as two separate registers.

It could be possible to factor out the DMA common code by introducing
some hooks to cope with platform quirks, but this patch does not touch
that for now.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
mmc: sdhci-pci-dwc-mshc: synopsys dwc mshc support 2018-07-16T09:21:45+00:00 Prabu Thangamuthu Prabu.T@synopsys.com 2018-07-11T07:56:17+00:00 152f8204ffcd7b64aa6b36f39ee86fbce3f650b8 Synopsys has DWC MSHC controller on HPAS-DX platform connected using PCIe interface with SD card slot and eMMC device slots. This patch is to enable SD cards connected on this platform. As Clock generation logic is implemented using MMCM module of HAPS-DX platform, we have separate functions to control the MMCM to generate required clocks with respect to speed mode. Signed-off-by: Prabu Thangamuthu <prabu.t@synopsys.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> 
Synopsys has DWC MSHC controller on HPAS-DX platform connected using PCIe
interface with SD card slot and eMMC device slots. This patch is to
enable SD cards connected on this platform. As Clock generation logic
is implemented using MMCM module of HAPS-DX platform, we have separate
functions to control the MMCM to generate required clocks with respect
to speed mode.

Signed-off-by: Prabu Thangamuthu <prabu.t@synopsys.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>