linux.git/drivers/memory/tegra/mc.h, branch v7.1 Linux kernel source tree memory: tegra: Add MC error logging support for Tegra264 2026-03-07T17:02:48+00:00 Ketan Patil ketanp@nvidia.com 2026-02-26T16:31:15+00:00 82169065ffb07577075a5088b313d78673ded331 In Tegra264, different components from memory subsystems like Memory Controller Fabric (MCF), HUB, HUB Common (HUBC), Side Band Shim (SBS) and channels have different interrupt lines for receiving memory controller error interrupts. Add support for logging memory controller errors reported by these memory subsystems on Tegra264 by: - Renaming tegra_mc_error_names array to tegra20_mc_error_names because it has a different bit index for error names compared to Tegra264. - Defining the intmask registers and mask values supported for Tegra264. - Registering interrupt handlers for interrupts associated with these different MC components which read the interrupt status registers to determine the type of violation that occurred. Signed-off-by: Ketan Patil <ketanp@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20260226163115.1152181-7-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> 
In Tegra264, different components from memory subsystems like Memory
Controller Fabric (MCF), HUB, HUB Common (HUBC), Side Band Shim (SBS)
and channels have different interrupt lines for receiving memory
controller error interrupts.

Add support for logging memory controller errors reported by these
memory subsystems on Tegra264 by:
- Renaming tegra_mc_error_names array to tegra20_mc_error_names
  because it has a different bit index for error names compared to
  Tegra264.
- Defining the intmask registers and mask values supported for
  Tegra264.
- Registering interrupt handlers for interrupts associated with these
  different MC components which read the interrupt status registers to
  determine the type of violation that occurred.

Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260226163115.1152181-7-ketanp@nvidia.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
memory: tegra: Group SoC specific fields 2026-03-07T17:02:29+00:00 Ketan Patil ketanp@nvidia.com 2026-02-26T16:31:13+00:00 2e4cfaa78eb98d2623367818c859225c6b6bf701 Introduce new SoC specific fields in tegra_mc_soc struct for high address mask and error status type mask because Tegra264 has different values for these than the existing devices. Error status registers e.g. MC_ERR_STATUS_0 has few bits which indicate the type of the error. In order to obtain such type of error from error status register, we use error status type mask. Similarly, these error status registers have bits which indicate the higher address bits of the address responsible for mc error. In order to obtain such higher address, we use high address mask. Make this change to prepare for adding MC interrupt support for Tegra264. Signed-off-by: Ketan Patil <ketanp@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20260226163115.1152181-5-ketanp@nvidia.com [krzk: Fix checkpatch warning] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> 
Introduce new SoC specific fields in tegra_mc_soc struct for high
address mask and error status type mask because Tegra264 has different
values for these than the existing devices. Error status registers
e.g. MC_ERR_STATUS_0 has few bits which indicate the type of the
error. In order to obtain such type of error from error status
register, we use error status type mask. Similarly, these error status
registers have bits which indicate the higher address bits of the
address responsible for mc error. In order to obtain such higher
address, we use high address mask. Make this change to prepare for
adding MC interrupt support for Tegra264.

Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260226163115.1152181-5-ketanp@nvidia.com
[krzk: Fix checkpatch warning]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
memory: tegra: Add support for multiple IRQs 2026-03-07T16:59:37+00:00 Ketan Patil ketanp@nvidia.com 2026-02-26T16:31:12+00:00 4d865a2374037d2d0842f88822fd753f0918b370 Add support to handle multiple MC interrupts lines, as supported by Tegra264. Turn the single IRQ handler callback into a counted array to allow specifying a separate handler for each interrupt. Move IRQ handlers into tegra_mc_soc struct, so as to specify SoC specific values. Signed-off-by: Ketan Patil <ketanp@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20260226163115.1152181-4-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> 
Add support to handle multiple MC interrupts lines, as supported by
Tegra264. Turn the single IRQ handler callback into a counted array to
allow specifying a separate handler for each interrupt. Move IRQ
handlers into tegra_mc_soc struct, so as to specify SoC specific
values.

Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260226163115.1152181-4-ketanp@nvidia.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
memory: tegra: Group register and fields 2026-03-07T16:59:36+00:00 Ketan Patil ketanp@nvidia.com 2026-02-26T16:31:11+00:00 95b714bd8c39d65b241aa1c346625b9c942af403 The current register definitions are not in sorted order. Sort these registers according to their address. Put bit fields and masks of the corresponding registers below the register definitions to clearly identify which fields belongs to which registers. Signed-off-by: Ketan Patil <ketanp@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20260226163115.1152181-3-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> 
The current register definitions are not in sorted order. Sort these
registers according to their address. Put bit fields and masks of the
corresponding registers below the register definitions to clearly
identify which fields belongs to which registers.

Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260226163115.1152181-3-ketanp@nvidia.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
memory: tegra: Group error handling related registers 2026-03-07T16:59:35+00:00 Ketan Patil ketanp@nvidia.com 2026-02-26T16:31:10+00:00 b8a177f18df1b439aac708da2d8bd9fcd68bb1eb Group MC error related registers into a struct as they could have SoC specific values. Tegra264 has different register offsets than the existing devices and so in order to add support for Tegra264 we need to first make this change. Signed-off-by: Ketan Patil <ketanp@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20260226163115.1152181-2-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> 
Group MC error related registers into a struct as they could have SoC
specific values. Tegra264 has different register offsets than the
existing devices and so in order to add support for Tegra264 we need to
first make this change.

Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260226163115.1152181-2-ketanp@nvidia.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
memory: tegra: Add Tegra264 MC and EMC support 2025-07-11T14:49:42+00:00 Sumit Gupta sumitg@nvidia.com 2025-07-09T22:21:47+00:00 2401dc4dcdd02920faa9a8c4384f1503a15e779a Add support to enable Memory Controller (MC) and External Memory Controller (EMC) drivers for Tegra264. The nodes for MC and EMC are mostly the same as Tegra234 but differ in number of channels and interrupt numbers. The patch also adds the bandwidth manager definitions required for Tegra264 and uses them to populate the memory client table. All of these are needed to properly enable memory interconnect (ICC) support. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250709222147.3758356-3-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com> 
Add support to enable Memory Controller (MC) and External Memory
Controller (EMC) drivers for Tegra264. The nodes for MC and EMC are
mostly the same as Tegra234 but differ in number of channels and
interrupt numbers.

The patch also adds the bandwidth manager definitions required for
Tegra264 and uses them to populate the memory client table. All of
these are needed to properly enable memory interconnect (ICC) support.

Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250709222147.3758356-3-thierry.reding@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Make CPU cluster BW request a multiple of MC channels 2023-05-16T10:11:01+00:00 Sumit Gupta sumitg@nvidia.com 2023-05-11T17:32:08+00:00 e852af72a7f21f4d25994365af86a92438d68014 Make CPU cluster's bandwidth (BW) request a multiple of MC channels. CPU OPP tables have BW info per MC channel. But, the actual BW depends on the number of MC channels which can change as per the boot config. Get the number of MC channels which are actually enabled in current boot configuration and multiply the BW request from a CPU cluster with the number of enabled MC channels. This is not required to be done for other MC clients. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Make CPU cluster's bandwidth (BW) request a multiple of MC channels.
CPU OPP tables have BW info per MC channel. But, the actual BW depends
on the number of MC channels which can change as per the boot config.
Get the number of MC channels which are actually enabled in current
boot configuration and multiply the BW request from a CPU cluster with
the number of enabled MC channels. This is not required to be done for
other MC clients.

Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Add MC error logging on Tegra186 onward 2022-05-09T08:46:14+00:00 Ashish Mhetre amhetre@nvidia.com 2022-05-06T13:23:12+00:00 54a85e09f44c5fa322a2d186f50862d09f517225 Add support for logging memory controller errors on Tegra186, Tegra194 and Tegra234. On these SoCs, interrupts can occur on multiple channels. Add support required to read the status of interrupts across multiple channels, log and clear them. Also add new interrupts supported on these SoCs. Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20220506132312.3910637-5-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 
Add support for logging memory controller errors on Tegra186, Tegra194
and Tegra234. On these SoCs, interrupts can occur on multiple channels.
Add support required to read the status of interrupts across multiple
channels, log and clear them.

Also add new interrupts supported on these SoCs.

Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20220506132312.3910637-5-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
memory: tegra: Add Tegra234 support 2022-05-09T08:46:00+00:00 Thierry Reding treding@nvidia.com 2022-05-06T13:23:09+00:00 72c81bb67026a07d7cd40418520269e12f0657cb The memory controller and external memory controller found on Tegra234 is similar to the version found on earlier SoCs but supports a number of new memory clients. Add initial memory client definitions for the Tegra234 so that the SMMU stream ID override registers can be properly programmed at boot time. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20220506132312.3910637-2-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 
The memory controller and external memory controller found on Tegra234
is similar to the version found on earlier SoCs but supports a number of
new memory clients.

Add initial memory client definitions for the Tegra234 so that the SMMU
stream ID override registers can be properly programmed at boot time.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20220506132312.3910637-2-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
memory: tegra: Split Tegra194 data into separate file 2021-06-03T19:49:41+00:00 Thierry Reding treding@nvidia.com 2021-06-02T16:33:02+00:00 8fd9f632ba93c0291a73be25ddd3f22631cd1052 Keep the directory structure consistent by splitting the Tegra194 data into a separate file. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210602163302.120041-13-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 
Keep the directory structure consistent by splitting the Tegra194 data
into a separate file.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210602163302.120041-13-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>