linux.git/drivers/memory/tegra/mc.c, branch v5.2-rc2 Linux kernel source tree memory: tegra: Replace readl-writel with mc_readl-mc_writel 2019-04-18T09:36:10+00:00 Dmitry Osipenko digetx@gmail.com 2019-04-11T22:12:49+00:00 48791f972234301a72e4c40745d0abafa0985d2d There is no need for a memory barriers on reading/writing of register values as we only care about the read/write order, hence let's use the common helpers. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
There is no need for a memory barriers on reading/writing of register
values as we only care about the read/write order, hence let's use the
common helpers.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Fix integer overflow on tick value calculation 2019-04-18T09:35:55+00:00 Dmitry Osipenko digetx@gmail.com 2019-04-11T22:12:48+00:00 b906c056b6023c390f18347169071193fda57dde Multiplying the Memory Controller clock rate by the tick count results in an integer overflow and in result the truncated tick value is being programmed into hardware, such that the GR3D memory client performance is reduced by two times. Cc: stable <stable@vger.kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Multiplying the Memory Controller clock rate by the tick count results
in an integer overflow and in result the truncated tick value is being
programmed into hardware, such that the GR3D memory client performance is
reduced by two times.

Cc: stable <stable@vger.kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Fix missed registers values latching 2019-04-18T09:35:38+00:00 Dmitry Osipenko digetx@gmail.com 2019-04-11T22:12:47+00:00 76b959a44c0b9c60cd41627cecb022c78042ad74 Some of Memory Controller registers are shadowed and require latching in order to copy assembly state into the active, MC_EMEM_ARB_CFG is one of these registers. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Some of Memory Controller registers are shadowed and require latching in
order to copy assembly state into the active, MC_EMEM_ARB_CFG is one of
these registers.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Properly spell "tegra" 2019-04-11T15:58:41+00:00 Thierry Reding treding@nvidia.com 2019-04-11T08:48:25+00:00 cb2b58391e40d0877b1f60023c8be72696ff8511 Rename all occurrences of "terga" to "tegra". It's an easy typo to make and a difficult one to spot. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Rename all occurrences of "terga" to "tegra". It's an easy typo to make
and a difficult one to spot.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Clean up error messages 2019-01-16T12:54:13+00:00 Dmitry Osipenko digetx@gmail.com 2018-12-12T20:38:59+00:00 f2dcded1be0d024870b5a4ef8e4a587857f303b4 Make all messages to start with a lower case and don't unnecessarily go over 80 chars in the code. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> 
Make all messages to start with a lower case and don't unnecessarily go
over 80 chars in the code.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
memory: tegra: Do not ask for IRQ sharing 2019-01-16T12:54:13+00:00 Dmitry Osipenko digetx@gmail.com 2018-12-12T20:38:58+00:00 33ea002aadd9cbf1836a13c71e424f113bce635a Memory Controller driver never shared IRQ with any other driver and very unlikely that it will. Hence there is no need to request IRQ sharing and the corresponding flag can be dropped safely. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> 
Memory Controller driver never shared IRQ with any other driver and very
unlikely that it will. Hence there is no need to request IRQ sharing and
the corresponding flag can be dropped safely.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
memory: tegra: Do not try to probe SMMU on Tegra20 2019-01-16T12:54:13+00:00 Dmitry Osipenko digetx@gmail.com 2018-12-12T20:38:57+00:00 568ece5bab24d41bec4d1610439277032840a133 Tegra20 doesn't have SMMU. Move out checking of the SMMU presence from the SMMU driver into the Memory Controller driver. This change makes code consistent in regards to how GART/SMMU presence checking is performed. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> 
Tegra20 doesn't have SMMU. Move out checking of the SMMU presence from
the SMMU driver into the Memory Controller driver. This change makes code
consistent in regards to how GART/SMMU presence checking is performed.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
iommu/tegra: gart: Integrate with Memory Controller driver 2019-01-16T12:54:12+00:00 Dmitry Osipenko digetx@gmail.com 2018-12-12T20:38:56+00:00 ce2785a75dbca27375f3723f4e697a2a8dc096ee The device-tree binding has been changed. There is no separate GART device anymore, it is squashed into the Memory Controller. Integrate GART module with the MC in a way it is done for the SMMU on Tegra30+. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> 
The device-tree binding has been changed. There is no separate GART device
anymore, it is squashed into the Memory Controller. Integrate GART module
with the MC in a way it is done for the SMMU on Tegra30+.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
memory: tegra: Use of_device_get_match_data() 2019-01-16T12:54:12+00:00 Dmitry Osipenko digetx@gmail.com 2018-12-12T20:38:54+00:00 59cd046f7f94543540d82216dbbfd8146db43b70 There is no need to match device with the DT node since it was already matched, use of_device_get_match_data() helper to get the match-data. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> 
There is no need to match device with the DT node since it was already
matched, use of_device_get_match_data() helper to get the match-data.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
memory: tegra: Read client ID on GART page fault 2019-01-16T12:54:11+00:00 Dmitry Osipenko digetx@gmail.com 2018-12-12T20:38:53+00:00 b3bb6b858f2a60fe3ac0c3833084386f7dd420e4 With the device tree binding changes, now Memory Controller has access to GART registers. Hence it is now possible to read client ID on GART page fault to get information about what memory client causes the fault. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> 
With the device tree binding changes, now Memory Controller has access to
GART registers. Hence it is now possible to read client ID on GART page
fault to get information about what memory client causes the fault.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>