linux.git/drivers/gpu, branch v4.19-rc3

drm/i915/dp_mst: Fix enabling pipe clock for all streams

2018-09-04T04:34:36+00:00

commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to encoders")
inadvertently stopped enabling the pipe clock for any DP-MST stream
after the first one. It also rearranged the pipe clock enabling wrt.
initial MST payload allocation step (which may or may not be a
problem, but it's contrary to the spec.).

Fix things by making the above commit truly a non-functional change.

Fixes: afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to encoders")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107365
Reported-by: Lyude Paul 
Reported-by: dmummenschanz@web.de
Tested-by: dmummenschanz@web.de
Tested-by: Lyude Paul 
Cc: Lyude Paul 
Cc: dmummenschanz@web.de
Cc: Ville Syrjälä 
Cc: Rodrigo Vivi 
Cc: Chris Wilson 
Signed-off-by: Imre Deak 
Reviewed-by: Ville Syrjälä 
Reviewed-by: Lyude Paul 
Reviewed-by: Rodrigo Vivi 
Link: https://patchwork.freedesktop.org/patch/msgid/20180831174739.30387-1-imre.deak@intel.com
(cherry picked from commit 2b5cf4ef541f1b2facaca58cae5e8e0b5f19ad4c)
Signed-off-by: Rodrigo Vivi

drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine

2018-09-04T04:31:36+00:00

This patch fixes the PPS4 and PPS5 register definition macros that were
resulting into an incorect MMIO address.

Fixes: 2efbb2f099fb ("i915/dp/dsc: Add DSC PPS register definitions")
Cc: Anusha Srivatsa 
Signed-off-by: Manasi Navare 
Reviewed-by: Rodrigo Vivi 
Reviewed-by: Anusha Srivatsa 
Link: https://patchwork.freedesktop.org/patch/msgid/20180824014807.14681-1-manasi.d.navare@intel.com
(cherry picked from commit 5df52391ddbed869c7d67b00fbb013bd64334115)
Signed-off-by: Rodrigo Vivi

drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse"

2018-09-04T04:31:28+00:00

This re-applies the workaround for "some DP sinks, [which] are a
little nuts" from commit 1a36147bb939 ("drm/i915: Perform link
quality check unconditionally during long pulse").
It makes the secondary AOC E2460P monitor connected via DP to an
acer Veriton N4640G usable again.

This hunk was dropped in commit c85d200e8321 ("drm/i915: Move SST
DP link retraining into the ->post_hotplug() hook")

Fixes: c85d200e8321 ("drm/i915: Move SST DP link retraining into the ->post_hotplug() hook")
[Cleaned up commit message, added stable cc]
Signed-off-by: Lyude Paul 
Signed-off-by: Jan-Marek Glogowski 
Cc: stable@vger.kernel.org
Link: https://patchwork.freedesktop.org/patch/msgid/20180825191035.3945-1-lyude@redhat.com
(cherry picked from commit 3cf71bc9904d7ee4a25a822c5dcb54c7804ea388)
Signed-off-by: Rodrigo Vivi

Merge tag 'gvt-fixes-2018-09-04' of https://github.com/intel/gvt-linux into drm-intel-fixes

2018-09-04T04:30:56+00:00

gvt-fixes-2018-09-04

- two BXT virtual display emulation fixes (Colin)
- gen9 dbuf guest warning fix (Xiaolin)
- vgpu close pm warning fix (Hang)
- dmabuf format_mod fix (Zhenyu)
- multiple VM guest failure fix for scheduling (Zhenyu)

Signed-off-by: Rodrigo Vivi 
From: Zhenyu Wang 
Link: https://patchwork.freedesktop.org/patch/msgid/20180904025437.GE20737@zhen-hp.sh.intel.com

drm/i915/gvt: Give new born vGPU higher scheduling chance

2018-09-03T06:28:23+00:00

This trys to give new born vGPU with higher scheduling chance
not only with adding to sched list head and also have higher
priority for workload sched for 2 seconds after starting to
schedule it. In order for fast GPU execution during VM boot,
and ensure guest driver setup with required state given in time.

This fixes recent failure seen on one VM with multiple linux VMs
running on kernel with commit 2621cefaa42b3("drm/i915: Provide a timeout to i915_gem_wait_for_idle() on setup"),
which had shorter setup timeout that caused context state init failed.

v2: change to 2s for higher scheduling period

Cc: Yuan Hang 
Reviewed-by: Hang Yuan 
Signed-off-by: Zhenyu Wang

drm/i915/gvt: Fix drm_format_mod value for vGPU plane

2018-08-30T04:56:33+00:00

Physical plane's tiling mode value is given directly as
drm_format_mod for plane query, which is not correct fourcc
code. Fix it by using correct intel tiling fourcc mod definition.

Current qemu seems also doesn't correctly utilize drm_format_mod
for plane object setting. Anyway this is required to fix the usage.

v3: use DRM_FORMAT_MOD_LINEAR, fix comment

v2: Fix missed old 'tiled' use for stride calculation

Fixes: e546e281d33d ("drm/i915/gvt: Dmabuf support for GVT-g")
Cc: Tina Zhang 
Cc: Gerd Hoffmann 
Cc: Colin Xu 
Reviewed-by: Colin Xu 
Signed-off-by: Zhenyu Wang

drm/i915/gvt: move intel_runtime_pm_get out of spin_lock in stop_schedule

2018-08-30T04:54:32+00:00

pm_runtime_get_sync in intel_runtime_pm_get might sleep if i915
device is not active. When stop vgpu schedule, the device may be
inactive. So need to move runtime_pm_get out of spin_lock/unlock.

Fixes: b24881e0b0b6("drm/i915/gvt: Add runtime_pm_get/put into gvt_switch_mmio
Cc: 
Signed-off-by: Hang Yuan 
Signed-off-by: Xiong Zhang 
Signed-off-by: Zhenyu Wang

drm/i915/gvt: Handle GEN9_WM_CHICKEN3 with F_CMD_ACCESS.

2018-08-30T04:54:09+00:00

Recent patch introduce strict check on scanning cmd:
Commit 8d458ea0ec33 ("drm/i915/gvt: return error on cmd access")

Before 8d458ea0ec33, if cmd_reg_handler() checks that a cmd access a mmio
that not marked as F_CMD_ACCESS, it simply returns 0 and log an error.
Now it will return -EBADRQC which will cause the workload fail to submit.

On BXT, i915 applies WaClearHIZ_WM_CHICKEN3 which will program
GEN9_WM_CHICKEN3 by LRI when init wa ctx. If it has no F_CMD_ACCESS flag,
vgpu will fail to start. Also add F_MODE_MASK since it's mode mask reg.

v2: Refresh commit message to elaborate issue symptom in detail.
v3: Make SKL_PLUS share same handling since GEN9_WM_CHICKEN3 should be
    F_CMD_ACCESS from HW aspect. (yan, zhenyu)

Signed-off-by: Colin Xu 
Acked-by: Zhao Yan 
Signed-off-by: Zhenyu Wang

drm/i915/gvt: Make correct handling to vreg BXT_PHY_CTL_FAMILY

2018-08-30T04:54:08+00:00

Guest kernel will write to BXT_PHY_CTL_FAMILY to reset DDI PHY
and pull BXT_PHY_CTL to check PHY status. Previous handling will
set/reset BXT_PHY_CTL of all PHYs at same time on receiving vreg
write to some BXT_PHY_CTL_FAMILY. If some BXT_PHY_CTL is already
enabled, following reset to another BXT_PHY_CTL_FAMILY will clear
the enabled BXT_PHY_CTL, which result in guest kernel print:

-----------------------------------
[drm:intel_ddi_get_hw_state [i915]]
*ERROR* Port B enabled but PHY powered down? (PHY_CTL 00000000)
-----------------------------------

The correct handling should operate BXT_PHY_CTL_FAMILY and
BXT_PHY_CTL on the same DDI.

v2: Use correct reg define. The naming looks confusing, however
    current i915_reg.h bind DPIO_PHY0 to _PHY_CTL_FAMILY_DDI and
    bind DPIO_PHY1 to _PHY_CTL_FAMILY_EDP, pairing to
    _BXT_PHY_CTL_DDI_A and _BXT_PHY_CTL_DDI_B respectively.
v3: v2 incorrectly map _PHY_CTL_FAMILY_EDP to _BXT_PHY_CTL_DDI_A.
    BXT_PHY_CTL() looks up DDI using PORTx but not PHYx. Based on
    DPIO_PHY to DDI mapping, make correct vreg handle to BXT_PHY_CTL
    on receiving vreg write to BXT_PHY_CTL_FAMILY. (He, Min)

Current mapping according to bxt_power_wells:
dpio-common-a:
    >>> DPIO_PHY1
    >>> BXT_DPIO_CMN_A_POWER_DOMAINS
    >>> POWER_DOMAIN_PORT_DDI_A_LANES
    >>> PORT_A

dpio-common-bc:
    >>> DPIO_PHY0
    >>> BXT_DPIO_CMN_BC_POWER_DOMAINS
    >>> POWER_DOMAIN_PORT_DDI_B_LANES | POWER_DOMAIN_PORT_DDI_C_LANES
    >>> PORT_B or PORT_C

Signed-off-by: Colin Xu 
Reviewed-by: He, Min 
Signed-off-by: Zhenyu Wang

drm/i915/gvt: emulate gen9 dbuf ctl register access

2018-08-30T04:54:08+00:00

there is below call track at boot time when booting guest
with kabylake vgpu with specifal configuration and this try to fix it.

[drm:gen9_dbuf_enable [i915]] *ERROR* DBuf power enable timeout
------------[ cut here ]------------
WARNING: gen9_dc_off_power_well_enable+0x224/0x230 [i915]
Unexpected DBuf power power state (0x8000000a)
Hardware name: Red Hat KVM, BIOS 1.11.0-2.el7 04/01/2014
Call Trace:
 [] dump_stack+0x19/0x1b
 [] __warn+0xd8/0x100
 [] warn_slowpath_fmt+0x5f/0x80
 [] gen9_dc_off_power_well_enable+0x224/0x230 [i915]
 [] intel_power_well_enable+0x42/0x50 [i915]
 [] __intel_display_power_get_domain+0x8a/0xb0 [i915]
 [] intel_display_power_get+0x33/0x50 [i915]
 [] intel_display_set_init_power+0x45/0x50 [i915]
 [] intel_power_domains_init_hw+0x63/0x8a0 [i915]
 [] i915_driver_load+0xae3/0x1760 [i915]
 [] ? nvmem_register+0x500/0x500
 [] i915_pci_probe+0x2c/0x50 [i915]
 [] local_pci_probe+0x4a/0xb0
 [] pci_device_probe+0x109/0x160
 [] driver_probe_device+0xc5/0x3e0
 [] __driver_attach+0x93/0xa0
 [] ? __device_attach+0x50/0x50
 [] bus_for_each_dev+0x75/0xc0
 [] driver_attach+0x1e/0x20
 [] bus_add_driver+0x200/0x2d0
 [] driver_register+0x64/0xf0
 [] __pci_register_driver+0xa5/0xc0
 [] ? 0xffffffffc0928fff
 [] i915_init+0x59/0x5c [i915]
 [] do_one_initcall+0xba/0x240
 [] load_module+0x272c/0x2bc0
 [] ? ddebug_proc_write+0xf0/0xf0
 [] SyS_init_module+0xc5/0x110
 [] system_call_fastpath+0x1c/0x21

Signed-off-by: Xiaolin Zhang 

Signed-off-by: Zhenyu Wang