linux.git/drivers/gpu/nova-core/fb.rs, branch v7.3-rc2

rust: dma: rename dma_handle to dma_address

2026-08-06T20:54:39+00:00

The `dma_handle` naming is inherited from the C API, but what this
really describes is the device DMA address; everything named
`dma_handle` is actually a `dma_addr_t`.

This naming introduces some confusion on the Rust API side, as handles
are supposed to be opaque tokens, yet we were doing address computation
on values returned by `dma_handle`.

Rename `dma_handle` to `dma_address` while nova-core is still its only
user.

Suggested-by: John Hubbard 
Suggested-by: Danilo Krummrich 
Link: https://lore.kernel.org/all/DK75LUA4NLGI.3P29AIZQE20V2@kernel.org/
Signed-off-by: Alexandre Courbot 
Reviewed-by: Robin Murphy 
Link: https://patch.msgid.link/20260805-falcon-dma-projections-v2-2-4cc9f3f13ee9@nvidia.com
[ Rebase and fix up build failures due to newly introduced dma_handle()
  calls. - Danilo ]
Signed-off-by: Danilo Krummrich

gpu: nova-core: split FbLayout into FSP and non-FSP versions

2026-08-05T05:20:37+00:00

`FbLayout` is currently used for both pre and post FSP architectures. It
contains ranges for each region of framebuffer, but on post FSP
architectures, only the size is actually used. The region locations are
decided by ACR, which runs as part of the GSP-FMC, not by the driver.
The driver only provides the sizes. So, for post FSP architectures
`FbLayout` contains essentially guesses for the offsets. Instead, make
separate types so that we only store the information that's actually
needed, rather than keeping around offsets that may not be correct.

Signed-off-by: Eliot Courtney 
Link: https://patch.msgid.link/20260804-blackwell-fixes-v4-4-ac858b6a1935@nvidia.com
Signed-off-by: Alexandre Courbot

gpu: nova-core: return non-WPR heap size as u64 from HALs

2026-08-05T05:20:37+00:00

This is always immediately widened to u64, so just return it as a u64
from the beginning.

Signed-off-by: Eliot Courtney 
Link: https://patch.msgid.link/20260804-blackwell-fixes-v4-3-ac858b6a1935@nvidia.com
Signed-off-by: Alexandre Courbot

gpu: nova-core: rename heap size field

2026-08-05T05:20:36+00:00

This field is called non_wpr_heap_size everywhere else. Unify the name
to make it more obvious which heap it is.

Signed-off-by: Eliot Courtney 
Link: https://patch.msgid.link/20260804-blackwell-fixes-v4-2-ac858b6a1935@nvidia.com
Signed-off-by: Alexandre Courbot

gpu: nova-core: Move PFB registers definitions

2026-07-30T04:01:13+00:00

Move PFB registers definitions into fb module and update registers
visibility.

Suggested-by: Alexandre Courbot 
Suggested-by: Danilo Krummrich 
Signed-off-by: Antonin Malzieu Ridolfi 
Link: https://patch.msgid.link/20260727-nova-core-regs-split-v2-2-21b5e6e32ea5@nanonej.com
Signed-off-by: Alexandre Courbot

gpu: nova-core: Add function to query WPR2 range

2026-07-30T04:01:13+00:00

Create new function abstracting WPR2 region range query.
Refactor gsp hal tu102 to query the WPR2 region range using this new
function.

Suggested-by: Alexandre Courbot 
Signed-off-by: Antonin Malzieu Ridolfi 
Link: https://patch.msgid.link/20260727-nova-core-regs-split-v2-1-21b5e6e32ea5@nanonej.com
Signed-off-by: Alexandre Courbot

gpu: nova-core: reserve vGPU WPR2 heap

2026-07-23T23:16:02+00:00

GSP-RM needs a larger WPR2 heap when booting in vGPU mode. The heap size
is firmware-dependent, so it should come from the generated firmware
bindings instead of being open-coded in nova-core.

Pass the detected vGPU state into the framebuffer layout calculation. Keep
baremetal boots on the existing heap sizing path, and use the 570.144
vGPU default heap binding only when vGPU is enabled. The same state match
also sets the VF partition count, so disabled and invalid 0/1-VF states do
not enter the vGPU heap path.

Cc: Alexandre Courbot 
Signed-off-by: Zhi Wang 
Reviewed-by: Alexandre Courbot 
Link: https://patch.msgid.link/20260722073913.1807677-7-zhiw@nvidia.com
[ Use checked arithmetic to calculate wpr2_heap_addr. - Danilo ]
Signed-off-by: Danilo Krummrich

gpu: nova-core: fb: Move PDISP register definition

2026-06-23T06:13:19+00:00

Move PDISP register definition into fb module and update register
visibility.

Signed-off-by: Antonin Malzieu Ridolfi 
Link: https://patch.msgid.link/20260617-nova-core-regs-split-v1-1-4c7dc4450ea7@nanonej.com
[acourbot: fix rustfmt issue.]
Signed-off-by: Alexandre Courbot

gpu: nova-core: move lifetime to `Bar0`

2026-06-03T20:10:51+00:00

Currently Nova code uses `&'a Bar0` a lot. This is `&'a Mmio`, where `Mmio`
represents an owned MMIO region; this type only exists as a target for
`Deref` so `Bar` and `IoMem` can share code and should be avoided to be
named directly. The upcoming I/O projection series would make `Io` trait
much simpler to implement, and thus the owned MMIO type would be removed
in favour of direct `Io` implementation on `Bar` and `IoMem`.

Add lifetime parameter to `Bar0<'a>` and change it to be alias of `&'a
pci::Bar<'a, ..>`. This also prepares Nova core so that when I/O projection
series land, this could be changed to using a MMIO view type directly which
avoids double indirection.

Signed-off-by: Gary Guo 
Acked-by: Alexandre Courbot 
Reviewed-by: Eliot Courtney 
Link: https://patch.msgid.link/20260602170416.2268531-1-gary@kernel.org
[ Rebase onto latest drm-rust-next (Blackwell enablement). - Danilo ]
Signed-off-by: Danilo Krummrich

gpu: nova-core: Hopper/Blackwell: larger non-WPR heap

2026-06-02T13:33:15+00:00

Hopper and Blackwell need a larger non-WPR heap than the 1 MiB that
earlier architectures use. Hopper and Blackwell GB10x need 2 MiB, while
Blackwell GB20x needs 2 MiB + 128 KiB. These sizes diverge by family,
so give Hopper and each Blackwell family its own framebuffer HAL and
select the non-WPR heap size per chipset family.

Signed-off-by: John Hubbard 
Reviewed-by: Eliot Courtney 
Link: https://patch.msgid.link/20260602032111.224790-5-jhubbard@nvidia.com
Signed-off-by: Alexandre Courbot