linux.git/drivers/gpu/host1x, branch v4.5-rc2 Linux kernel source tree gpu: host1x: Add Tegra210 support 2015-12-14T09:50:33+00:00 Thierry Reding treding@nvidia.com 2015-03-23T09:46:28+00:00 a134789a67480e6cc7e50c9dfcbc7adca5016010 The host1x unit found in Tegra210 SoCs is very similar to the unit in Tegra124, but it has 2 additional channels for a total of 14 channels. Signed-off-by: Thierry Reding <treding@nvidia.com> 
The host1x unit found in Tegra210 SoCs is very similar to the unit in
Tegra124, but it has 2 additional channels for a total of 14 channels.

Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Remove core driver on unregister 2015-12-14T09:50:33+00:00 Thierry Reding treding@nvidia.com 2015-08-24T12:51:04+00:00 e3e70814cebb0beec47dd38e60f89850950a2903 When unregistering a host1x driver, make sure to unregister the core driver as well to prevent it from sticking around and oppose reloading of the driver. Signed-off-by: Thierry Reding <treding@nvidia.com> 
When unregistering a host1x driver, make sure to unregister the core
driver as well to prevent it from sticking around and oppose reloading
of the driver.

Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Use platform_register/unregister_drivers() 2015-12-14T09:50:32+00:00 Thierry Reding treding@nvidia.com 2015-12-02T16:24:20+00:00 28fae81f93d5482f25bb8e9881104ad1157c2cfd These new helpers simplify implementing multi-driver modules and properly handle failure to register one driver by unregistering all previously registered drivers. Signed-off-by: Thierry Reding <treding@nvidia.com> 
These new helpers simplify implementing multi-driver modules and
properly handle failure to register one driver by unregistering all
previously registered drivers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Fix MLOCK's debug info 2015-10-02T12:40:12+00:00 Dmitry Osipenko digetx@gmail.com 2015-06-28T19:27:02+00:00 3fe2c7d4c85b4557c9772ff16f31ddc18cfd2521 MLOCK's debug info, spewed on CDMA timeout, contains meaningless MLOCK owner channel ID because HOST1X_SYNC_MLOCK_OWNER_CHID_F() returns shifted value, while unshifted should be used. Fix it by changing '_F' to '_V'. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-By: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
MLOCK's debug info, spewed on CDMA timeout, contains meaningless MLOCK
owner channel ID because HOST1X_SYNC_MLOCK_OWNER_CHID_F() returns shifted
value, while unshifted should be used. Fix it by changing '_F' to '_V'.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-By: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: mipi: Power down regulators when unused 2015-08-13T11:47:21+00:00 Thierry Reding treding@nvidia.com 2015-04-10T09:29:41+00:00 15372d4be7f099662dc84e4e35e844bd4373d959 Keep track of the number of users of DSI and CSI pads and power down the regulators that supply the bricks when all users are gone. Signed-off-by: Thierry Reding <treding@nvidia.com> 
Keep track of the number of users of DSI and CSI pads and power down the
regulators that supply the bricks when all users are gone.

Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: mipi: Add Tegra210 support 2015-08-13T11:47:20+00:00 Thierry Reding treding@nvidia.com 2015-04-08T15:23:20+00:00 5e7752436e10427ba598de4f2f6b7889daf586cc Some changes are needed to the configuration settings for some lanes. In addition, the clock lanes for the CSI pads can no longer be calibrated. Signed-off-by: Thierry Reding <treding@nvidia.com> 
Some changes are needed to the configuration settings for some lanes. In
addition, the clock lanes for the CSI pads can no longer be calibrated.

Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: mipi: Add Tegra132 support 2015-08-13T11:47:19+00:00 Thierry Reding treding@nvidia.com 2015-04-08T15:20:32+00:00 7fd3ecad3f768fd2b39fc4db12044437fbf5d735 While Tegra132 has the same pads as Tegra124, some configuration values need to be programmed slightly differently. Signed-off-by: Thierry Reding <treding@nvidia.com> 
While Tegra132 has the same pads as Tegra124, some configuration values
need to be programmed slightly differently.

Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: mipi: Constify OF match table 2015-08-13T11:47:18+00:00 Thierry Reding treding@nvidia.com 2015-04-08T15:19:19+00:00 c22fb79099dbec82b8280106c43f6e800ecc854c This table is never modified and can therefore reside in read-only memory. Signed-off-by: Thierry Reding <treding@nvidia.com> 
This table is never modified and can therefore reside in read-only
memory.

Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: mipi: Clear calibration status 2015-08-13T11:47:17+00:00 Thierry Reding treding@nvidia.com 2015-04-08T15:17:44+00:00 2ed264bf916b689fe0c71ac726995f0876062667 Before starting a new calibration cycle, make sure to clear the current status by writing a 1 to the various "calibration done" bits. Signed-off-by: Thierry Reding <treding@nvidia.com> 
Before starting a new calibration cycle, make sure to clear the current
status by writing a 1 to the various "calibration done" bits.

Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: mipi: Fix clock lane register for DSI 2015-08-13T11:47:16+00:00 Thierry Reding treding@nvidia.com 2015-04-08T15:06:08+00:00 8ed5c0623272663783e052123fea02651464a0a5 Use more consistent names for the clock lane configuration registers and fix the offset of the upper clock lane configuration register for the first DSI pad. Signed-off-by: Thierry Reding <treding@nvidia.com> 
Use more consistent names for the clock lane configuration registers and
fix the offset of the upper clock lane configuration register for the
first DSI pad.

Signed-off-by: Thierry Reding <treding@nvidia.com>