linux.git/drivers/gpu/drm/xe/xe_sysctrl.c, branch v7.3-rc2 Linux kernel source tree drm/xe/sysctrl: Read mailbox phase bit from hardware 2026-08-27T16:00:17+00:00 Anoop Vijay anoop.c.vijay@intel.com 2026-08-25T17:28:28+00:00 a62212b35a214c2ff3bd1c785a440d7ad8205ec9 The mailbox PHASE bit in SYSCTRL_MB_CTRL is toggled per-message and was tracked in software as sc->phase_bit, reset to 0 on error paths. If the cached value ever drifts from what the hardware last saw, all following messages carry the wrong phase and get silently misread by firmware. Drop the cache and read PHASE directly from SYSCTRL_MB_CTRL before each frame instead, removing xe_sysctrl_mailbox_init() and its call sites along with it. Fixes: 1f95f618182b ("drm/xe/xe_sysctrl: Add System Controller mailbox communication support") Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/20260825172827.3801591-2-anoop.c.vijay@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (cherry picked from commit 04984fcdbf6876c940c01026a7404c1e9cc91ba7) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> 
The mailbox PHASE bit in SYSCTRL_MB_CTRL is toggled per-message and
was tracked in software as sc->phase_bit, reset to 0 on error paths.
If the cached value ever drifts from what the hardware last saw, all
following messages carry the wrong phase and get silently misread by
firmware.

Drop the cache and read PHASE directly from SYSCTRL_MB_CTRL before
each frame instead, removing xe_sysctrl_mailbox_init() and its call
sites along with it.

Fixes: 1f95f618182b ("drm/xe/xe_sysctrl: Add System Controller mailbox communication support")
Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/20260825172827.3801591-2-anoop.c.vijay@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
(cherry picked from commit 04984fcdbf6876c940c01026a7404c1e9cc91ba7)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drm/xe/sysctrl: Add system controller event support 2026-04-30T06:01:45+00:00 Raag Jadav raag.jadav@intel.com 2026-04-28T05:48:25+00:00 21677c5ea98ac16657c572b4a0dee6893ecda1c6 System controller reports different types of events to GFX endpoint for different usecases, add initial support for them. This will be further extended to service those usecases. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com> Link: https://patch.msgid.link/20260428054826.1202076-3-raag.jadav@intel.com Signed-off-by: Riana Tauro <riana.tauro@intel.com> 
System controller reports different types of events to GFX endpoint for
different usecases, add initial support for them. This will be further
extended to service those usecases.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
Link: https://patch.msgid.link/20260428054826.1202076-3-raag.jadav@intel.com
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
drm/xe/sysctrl: Add system controller interrupt handler 2026-04-30T06:01:45+00:00 Raag Jadav raag.jadav@intel.com 2026-04-28T05:48:24+00:00 a68247371b6eb33013429037b28ff713aa60fc5a Add system controller interrupt handler which is denoted by 11th bit in GFX master interrupt register. While at it, add worker for scheduling system controller work. Co-developed-by: Soham Purkait <soham.purkait@intel.com> Signed-off-by: Soham Purkait <soham.purkait@intel.com> Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Link: https://patch.msgid.link/20260428054826.1202076-2-raag.jadav@intel.com Signed-off-by: Riana Tauro <riana.tauro@intel.com> 
Add system controller interrupt handler which is denoted by 11th bit in
GFX master interrupt register. While at it, add worker for scheduling
system controller work.

Co-developed-by: Soham Purkait <soham.purkait@intel.com>
Signed-off-by: Soham Purkait <soham.purkait@intel.com>
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
Link: https://patch.msgid.link/20260428054826.1202076-2-raag.jadav@intel.com
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
drm/xe/xe_sysctrl: Add System Controller power management support 2026-03-30T17:06:55+00:00 Anoop Vijay anoop.c.vijay@intel.com 2026-03-27T13:18:43+00:00 02eca6edcb324bc37495930c344e235a90f42d72 Add resume handling for System Controller to support system (S3/S4) and runtime power management transitions. On resume, restore SoC remapper configuration and mailbox interface to re‑establish communication with firmware. Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by: Badal Nilawar <badal.nilawar@intel.com> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Link: https://patch.msgid.link/20260327131837.2192929-15-anoop.c.vijay@intel.com 
Add resume handling for System Controller to support system (S3/S4) and
runtime power management transitions.

On resume, restore SoC remapper configuration and mailbox interface to
re‑establish communication with firmware.

Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://patch.msgid.link/20260327131837.2192929-15-anoop.c.vijay@intel.com
drm/xe/xe_sysctrl: Add System Controller mailbox communication support 2026-03-30T17:06:55+00:00 Anoop Vijay anoop.c.vijay@intel.com 2026-03-27T13:18:42+00:00 1f95f618182b5c99d46378141e0fb84f09bf914b Add mailbox communication layer required for interacting with System Controller firmware, enabling command submission and response handling. This patch implements command/response handling logic, including error and timeout handling. Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Link: https://patch.msgid.link/20260327131837.2192929-14-anoop.c.vijay@intel.com 
Add mailbox communication layer required for interacting with System
Controller firmware, enabling command submission and response handling.

This patch implements command/response handling logic, including error
and timeout handling.

Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://patch.msgid.link/20260327131837.2192929-14-anoop.c.vijay@intel.com
drm/xe/xe_sysctrl: Add System Controller initialization support 2026-03-30T17:06:55+00:00 Anoop Vijay anoop.c.vijay@intel.com 2026-03-27T13:18:41+00:00 5ea3f0dc8f9d33adf72532b366d0b7b91dae4d7f Add initialization and cleanup infrastructure for System Controller subsystem and integrate it into xe device probe path. During initialization, platform support is checked via has_sysctrl capability flag and the mailbox region is configured through SoC remapper interface. Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Link: https://patch.msgid.link/20260327131837.2192929-13-anoop.c.vijay@intel.com 
Add initialization and cleanup infrastructure for System Controller
subsystem and integrate it into xe device probe path.

During initialization, platform support is checked via has_sysctrl
capability flag and the mailbox region is configured through SoC
remapper interface.

Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://patch.msgid.link/20260327131837.2192929-13-anoop.c.vijay@intel.com