linux.git/drivers/gpu/drm/xe/xe_pcode.c, branch v7.3-rc2

drm/xe/pcode: Add support to get pcode version from PMT

2026-07-06T15:55:48+00:00

Add api get_pcode_version() to read pcode version from PMT telemetry.
Add PUNIT_VERSION telemetry offset in xe_pmt.h.

Signed-off-by: Karthik Poosa 
Reviewed-by: Michael J. Ruhl 
Link: https://patch.msgid.link/20260702092540.1005095-2-karthik.poosa@intel.com
Signed-off-by: Matt Roper

drm/xe/pcode: Don't ignore drmm_mutex_init failure

2026-06-01T13:45:21+00:00

The drm_device-managed mutex_init might fail and return an error.
Add proper error handling. While around, update the function name
to clearly indicate this is an early software-only initialization.

Signed-off-by: Michal Wajdeczko 
Reviewed-by: Rodrigo Vivi 
Link: https://patch.msgid.link/20260529195956.25349-1-michal.wajdeczko@intel.com

drm/{i915, xe}/pcode: move display pcode calls to parent interface

2026-01-27T14:45:53+00:00

Call the parent driver pcode functions through the parent interface
function pointers instead of expecting both to have functions of the
same name.

In i915, add the interface to existing intel_pcode.[ch], while in xe
move them to new display/xe_display_pcode.[ch] and build it only for
CONFIG_DRM_XE_DISPLAY=y.

Do not add separate write and write_timeout calls in the
interface. Instead, handle the default 1 ms timeout in the
intel_parent.c glue layer.

This drops the last intel_pcode.h includes from display, and allows us
to remove the corresponding xe compat header.

v2: initialize .pcode in i915

Reviewed-by: Michał Grzelak 
Link: https://patch.msgid.link/20260126112925.2452171-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula

drm/xe/pcode: Rework error mapping

2025-11-12T16:57:27+00:00

The sparse array used for error decoding from is unnecessarily big. It
should be better handled by a switch statement that will also allow us
to more easily improve this code.

Add a CASE_ERR() macro to keep the table compact and use it instead of
the 256-entries array, which saves some space:

	$ bloat-o-meter xe_pcode.o.old xe_pcode.o
	add/remove: 0/1 grow/shrink: 2/0 up/down: 190/-4096 (-3906)
	Function                                     old     new   delta
	__pcode_mailbox_rw                           363     465    +102
	__pcode_mailbox_rw.cold                       58     146     +88
	err_decode                                  4096       -   -4096
	Total: Before=7890, After=3984, chg -49.51%

Reviewed-by: Raag Jadav 
Link: https://patch.msgid.link/20251110-pcode-errmap-v2-1-cb18c8f54238@intel.com
Signed-off-by: Lucas De Marchi

drm/xe: Fix conflicting intel_pcode_* symbols

2025-06-28T13:56:58+00:00

If CONFIG_DRM_XE_DISPLAY is set, the xe module can only be built as
module to avoid duplicate symbols from i915. The interface for pcode was
added without considering that, so the build breaks if both xe and i915
are built-in.

Since the intel_pcode_* functions should only be called from the display
side (xe side should call the xe interface directly) and there's already
a protection in Kconfig to avoid the problematic configuration, ifdef it
out in case CONFIG_DRM_XE_DISPLAY is disabled.

Closes: https://lore.kernel.org/r/3667a992-a24b-4e49-aab2-5ca73f2c0a56@infradead.org
Fixes: d9465cc8ac2d ("drm/xe/pcode: add struct drm_device based interface")
Acked-by: Jani Nikula 
Reviewed-by: Randy Dunlap 
Tested-by: Randy Dunlap 
Reviewed-by: Rodrigo Vivi 
Link: https://lore.kernel.org/r/20250627-xe-kunit-v2-1-756fe5cd56cf@intel.com
Signed-off-by: Lucas De Marchi

drm/xe/pcode: add struct drm_device based interface

2025-06-23T18:45:16+00:00

In preparation for dropping the dependency on struct intel_uncore or
struct xe_tile from display code, add a struct drm_device based
interface to pcode.

Cc: Lucas De Marchi 
Cc: Rodrigo Vivi 
Reviewed-by: Rodrigo Vivi 
Link: https://lore.kernel.org/r/eeaa9cc8438caab2e22f9cb2142fbc18cc0fd861.1750678991.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula

drm/xe/hwmon: Add support to manage power limits though mailbox

2025-06-05T16:05:44+00:00

Add support to manage power limits using pcode mailbox commands
for supported platforms.

v2:
 - Address review comments. (Badal)
 - Use mailbox commands instead of registers to manage power limits
   for BMG.
 - Clamp the maximum power limit to GPU firmware default value.

v3:
 - Clamp power limit in write also for platforms with mailbox support.

v4:
 - Remove unnecessary debug prints. (Badal)

v5:
 - Update description of variable pl1_on_boot to fix kernel-doc error.

v6:
 - Improve commit message, refer to BIOS as GPU firmware.
 - Change macro READ_PL_FROM_BIOS to READ_PL_FROM_FW.
 - Rectify drm_warn to drm_info.

Signed-off-by: Karthik Poosa 
Fixes: e90f7a58e659 ("drm/xe/hwmon: Add HWMON support for BMG")
Reviewed-by: Badal Nilawar 
Link: https://lore.kernel.org/r/20250529163458.2354509-2-karthik.poosa@intel.com
Signed-off-by: Rodrigo Vivi 
(cherry picked from commit 7596d839f6228757fe17a810da2d1c5f3305078c)
Signed-off-by: Thomas Hellström

drm/xe: Allow to inject error in early probe

2025-03-21T18:48:22+00:00

Allow to test if driver behaves correctly when xe_pcode_probe_early()
fails. Note that this is not sufficient for testing survivability mode
as it's still required to read the hw to check for errors, which doesn't
happen on an injected failure.

To complete the early probe coverage, allow injection in the other
functions as well: xe_mmio_probe_early() and xe_device_probe_early().

Reviewed-by: Francois Dugast 
Link: https://patchwork.freedesktop.org/patch/msgid/20250314-fix-survivability-v5-3-fdb3559ea965@intel.com
Signed-off-by: Lucas De Marchi

drm/xe: Fix all typos in xe

2025-01-09T16:58:09+00:00

Fix all typos in files of xe, reported by codespell tool.

Signed-off-by: Nitin Gote 
Reviewed-by: Andi Shyti 
Reviewed-by: Stuart Summers 
Link: https://patchwork.freedesktop.org/patch/msgid/20250106102646.1400146-2-nitin.r.gote@intel.com
Signed-off-by: Nirmoy Das

drm/xe/pcode: Convert register access to use xe_mmio

2024-09-11T22:17:43+00:00

Stop using GT pointers for register access.  Although some of the pcode
mailboxes are related to GTs, pcode itself (and the register interface
to access it) are outside the GT and should be accessed through the
tile's MMIO.

Reviewed-by: Lucas De Marchi 
Signed-off-by: Matt Roper 
Link: https://patchwork.freedesktop.org/patch/msgid/20240910234719.3335472-56-matthew.d.roper@intel.com