<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/gpu/drm/xe/xe_pci_error.c, branch master</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>drm/xe/xe_pci_error: Process errors in mmio_enabled</title>
<updated>2026-07-15T05:26:21+00:00</updated>
<author>
<name>Riana Tauro</name>
<email>riana.tauro@intel.com</email>
</author>
<published>2026-07-13T07:48:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=acc744fa62fb098358f371bfb38e6b32032459c7'/>
<id>acc744fa62fb098358f371bfb38e6b32032459c7</id>
<content type='text'>
Query system controller when any non fatal error occurs to check
the type of the error, contain and recover.

The system controller is queried in the mmio_enabled callback.

Reviewed-by: Raag Jadav &lt;raag.jadav@intel.com&gt;
Reviewed-by: Mallesh Koujalagi &lt;mallesh.koujalagi@intel.com&gt;
Link: https://patch.msgid.link/20260713074755.1278607-10-riana.tauro@intel.com
Signed-off-by: Riana Tauro &lt;riana.tauro@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Query system controller when any non fatal error occurs to check
the type of the error, contain and recover.

The system controller is queried in the mmio_enabled callback.

Reviewed-by: Raag Jadav &lt;raag.jadav@intel.com&gt;
Reviewed-by: Mallesh Koujalagi &lt;mallesh.koujalagi@intel.com&gt;
Link: https://patch.msgid.link/20260713074755.1278607-10-riana.tauro@intel.com
Signed-off-by: Riana Tauro &lt;riana.tauro@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/xe: Skip device access during PCI error recovery</title>
<updated>2026-07-02T08:09:38+00:00</updated>
<author>
<name>Riana Tauro</name>
<email>riana.tauro@intel.com</email>
</author>
<published>2026-06-29T08:28:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=e46ee82f120f7f6ac4a2bf8ee6199ef65ceaea1a'/>
<id>e46ee82f120f7f6ac4a2bf8ee6199ef65ceaea1a</id>
<content type='text'>
When a fatal error occurs and the error_detected callback is
invoked the device is inaccessible. The error_detected callback
wedges the device causing the jobs to timeout.

The timedout handler acquires forcewake to dump devcoredump and
triggers a GT reset. Since the device is inaccessible this causes
errors. Skip all mmio accesses and gt reset when the device
is in reset.

Cc: Matthew Brost &lt;matthew.brost@intel.com&gt;
Cc: Himal Prasad Ghimiray &lt;himal.prasad.ghimiray@intel.com&gt;
Reviewed-by: Mallesh Koujalagi &lt;mallesh.koujalagi@intel.com&gt;
Link: https://patch.msgid.link/20260629082802.3690896-9-riana.tauro@intel.com
Signed-off-by: Riana Tauro &lt;riana.tauro@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When a fatal error occurs and the error_detected callback is
invoked the device is inaccessible. The error_detected callback
wedges the device causing the jobs to timeout.

The timedout handler acquires forcewake to dump devcoredump and
triggers a GT reset. Since the device is inaccessible this causes
errors. Skip all mmio accesses and gt reset when the device
is in reset.

Cc: Matthew Brost &lt;matthew.brost@intel.com&gt;
Cc: Himal Prasad Ghimiray &lt;himal.prasad.ghimiray@intel.com&gt;
Reviewed-by: Mallesh Koujalagi &lt;mallesh.koujalagi@intel.com&gt;
Link: https://patch.msgid.link/20260629082802.3690896-9-riana.tauro@intel.com
Signed-off-by: Riana Tauro &lt;riana.tauro@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/xe/xe_pci_error: Group all devres to release them on PCIe slot reset</title>
<updated>2026-07-02T08:09:38+00:00</updated>
<author>
<name>Riana Tauro</name>
<email>riana.tauro@intel.com</email>
</author>
<published>2026-06-29T08:28:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=0a0fae3327a537b23e86463240e7381ddb5e31a1'/>
<id>0a0fae3327a537b23e86463240e7381ddb5e31a1</id>
<content type='text'>
Add devres grouping to handle device resource cleanup during
PCI error recovery.

Secondary Bus Reset (SBR) is triggered by PCI core when the
error_detected/mmio_enabled callbacks return PCI_ERS_RESULT_NEED_RESET.

Once SBR is complete, the slot_reset callback is triggered. SBR wipes
out all device memory requiring XE KMD to perform a device removal and
reprobe.
Calling xe_pci_remove() alone does not free the devres allocated.
Since there are no exported functions to release all devres, group the
devres allocations and release the entire group during slot reset to
ensure proper cleanup.

Cc: Matthew Brost &lt;matthew.brost@intel.com&gt;
Cc: Himal Prasad Ghimiray &lt;himal.prasad.ghimiray@intel.com&gt;
Reviewed-by: Mallesh Koujalagi &lt;mallesh.koujalagi@intel.com&gt;
Link: https://patch.msgid.link/20260629082802.3690896-8-riana.tauro@intel.com
Signed-off-by: Riana Tauro &lt;riana.tauro@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add devres grouping to handle device resource cleanup during
PCI error recovery.

Secondary Bus Reset (SBR) is triggered by PCI core when the
error_detected/mmio_enabled callbacks return PCI_ERS_RESULT_NEED_RESET.

Once SBR is complete, the slot_reset callback is triggered. SBR wipes
out all device memory requiring XE KMD to perform a device removal and
reprobe.
Calling xe_pci_remove() alone does not free the devres allocated.
Since there are no exported functions to release all devres, group the
devres allocations and release the entire group during slot reset to
ensure proper cleanup.

Cc: Matthew Brost &lt;matthew.brost@intel.com&gt;
Cc: Himal Prasad Ghimiray &lt;himal.prasad.ghimiray@intel.com&gt;
Reviewed-by: Mallesh Koujalagi &lt;mallesh.koujalagi@intel.com&gt;
Link: https://patch.msgid.link/20260629082802.3690896-8-riana.tauro@intel.com
Signed-off-by: Riana Tauro &lt;riana.tauro@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/xe/xe_pci_error: Implement PCI error recovery callbacks</title>
<updated>2026-07-02T08:09:38+00:00</updated>
<author>
<name>Riana Tauro</name>
<email>riana.tauro@intel.com</email>
</author>
<published>2026-06-29T08:28:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=13b9555ffb0304d736fcad01e7a75d329b81ae9a'/>
<id>13b9555ffb0304d736fcad01e7a75d329b81ae9a</id>
<content type='text'>
Add error_detected, mmio_enabled, slot_reset and resume recovery callbacks
to handle PCIe Advanced Error Reporting (AER) errors.

For fatal errors, the device is wedged and becomes inaccessible. Return
PCI_ERS_RESULT_NEED_RESET from error_detected to request a Secondary
Bus Reset (SBR).

For non-fatal errors, return PCI_ERS_RESULT_CAN_RECOVER from
error_detected to trigger the mmio_enabled callback. In this callback, the
device is queried to determine the error cause and attempt recovery based
on the error type.

Once the secondary bus reset(SBR) is completed the slot_reset callback
cleanly removes and reprobe the device to restore functionality.

Cc: Matthew Brost &lt;matthew.brost@intel.com&gt;
Cc: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Reviewed-by: Mallesh Koujalagi &lt;mallesh.koujalagi@intel.com&gt;
Link: https://patch.msgid.link/20260629082802.3690896-7-riana.tauro@intel.com
Signed-off-by: Riana Tauro &lt;riana.tauro@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add error_detected, mmio_enabled, slot_reset and resume recovery callbacks
to handle PCIe Advanced Error Reporting (AER) errors.

For fatal errors, the device is wedged and becomes inaccessible. Return
PCI_ERS_RESULT_NEED_RESET from error_detected to request a Secondary
Bus Reset (SBR).

For non-fatal errors, return PCI_ERS_RESULT_CAN_RECOVER from
error_detected to trigger the mmio_enabled callback. In this callback, the
device is queried to determine the error cause and attempt recovery based
on the error type.

Once the secondary bus reset(SBR) is completed the slot_reset callback
cleanly removes and reprobe the device to restore functionality.

Cc: Matthew Brost &lt;matthew.brost@intel.com&gt;
Cc: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Reviewed-by: Mallesh Koujalagi &lt;mallesh.koujalagi@intel.com&gt;
Link: https://patch.msgid.link/20260629082802.3690896-7-riana.tauro@intel.com
Signed-off-by: Riana Tauro &lt;riana.tauro@intel.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
