linux.git/drivers/gpu/drm/xe/abi, branch master Linux kernel source tree drm/xe/guc: Formalize Reserved KLVs 2026-07-11T14:15:27+00:00 Michal Wajdeczko michal.wajdeczko@intel.com 2026-07-10T17:25:34+00:00 2963124ff9eb0d9be96dd38f43817e40ee32c31a We have already started using few KLV keys from the 0xF000 range that, as we have agreed with the GuC team, will not be used in any GuC ABI actions. Add definitions for that reserved range and move our migration KLVs to new ABI header. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Michał Winiarski <michal.winiarski@intel.com> Link: https://patch.msgid.link/20260710172534.7201-1-michal.wajdeczko@intel.com 
We have already started using few KLV keys from the 0xF000 range
that, as we have agreed with the GuC team, will not be used in any
GuC ABI actions. Add definitions for that reserved range and move
our migration KLVs to new ABI header.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Link: https://patch.msgid.link/20260710172534.7201-1-michal.wajdeczko@intel.com
drm/xe/configfs: Add enable_multi_queue attribute 2026-07-10T15:08:47+00:00 Shuicheng Lin shuicheng.lin@intel.com 2026-07-09T20:08:22+00:00 73c5a253068e8cdf975941a14f032e351730a396 Add a new configfs boolean attribute 'enable_multi_queue' that lets an administrator force-disable multi-queue support on a device before it binds to the driver. The attribute defaults to true (use the platform hardware capability as-is); writing 0 force-disables multi-queue. This is intended for debugging and for validating non-multi-queue code paths on hardware that would otherwise expose multi-queue. The override disables multi-queue at two levels: - UAPI: In alloc_primary_gt(), clear gt->info.multi_queue_engine_class_mask on the primary GT so that xe_gt_supports_multi_queue() returns false and attempts to create a multi-queue group via DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP are rejected. - GuC: In guc_ctl_feature_flags(), set the GUC_CTL_DISABLE_MULTI_QUEUE (BIT(24)) init-params bit on GuC firmware older than 70.66. On GuC firmware 70.66 and above, guc_waklv_init() emits the new GUC_FEATURE_KLV_DISABLE_MULTI_QUEUE Feature KLV (0x5001) via the ADS WA/Feature KLV buffer instead. Feature KLVs share the WA KLV buffer. The attribute is rejected after the device has been bound, so it only takes effect during probe: # echo 0 > /sys/kernel/config/xe/0000:03:00.0/enable_multi_queue # echo 0000:03:00.0 > /sys/bus/pci/drivers/xe/bind v2: Add log for multi-queue disabled. (Niranjana) v3: Rename attribute to enable_multi_queue with default true. (Stuart && Niranjana) v4: rebase. Assisted-by: Claude:claude-opus-4.7 Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Reviewed-by: Stuart Summers <stuart.summers@intel.com> Link: https://patch.msgid.link/20260709200822.3257825-1-shuicheng.lin@intel.com Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com> 
Add a new configfs boolean attribute 'enable_multi_queue' that lets an
administrator force-disable multi-queue support on a device before it
binds to the driver. The attribute defaults to true (use the platform
hardware capability as-is); writing 0 force-disables multi-queue. This
is intended for debugging and for validating non-multi-queue code paths
on hardware that would otherwise expose multi-queue.

The override disables multi-queue at two levels:

- UAPI: In alloc_primary_gt(), clear
  gt->info.multi_queue_engine_class_mask on the primary GT so that
  xe_gt_supports_multi_queue() returns false and attempts to create
  a multi-queue group via DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP
  are rejected.

- GuC: In guc_ctl_feature_flags(), set the GUC_CTL_DISABLE_MULTI_QUEUE
  (BIT(24)) init-params bit on GuC firmware older than 70.66. On GuC
  firmware 70.66 and above, guc_waklv_init() emits the new
  GUC_FEATURE_KLV_DISABLE_MULTI_QUEUE Feature KLV (0x5001) via the ADS
  WA/Feature KLV buffer instead. Feature KLVs share the WA KLV buffer.

The attribute is rejected after the device has been bound, so it only
takes effect during probe:

	# echo 0 > /sys/kernel/config/xe/0000:03:00.0/enable_multi_queue
	# echo 0000:03:00.0 > /sys/bus/pci/drivers/xe/bind

v2: Add log for multi-queue disabled. (Niranjana)
v3: Rename attribute to enable_multi_queue with default true. (Stuart &&
    Niranjana)
v4: rebase.

Assisted-by: Claude:claude-opus-4.7
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Link: https://patch.msgid.link/20260709200822.3257825-1-shuicheng.lin@intel.com
Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com>
drm/xe/vf: wire up NUM_PAGING_ENGINE_INSTANCES 2026-07-10T11:50:19+00:00 Matthew Auld matthew.auld@intel.com 2026-06-26T11:15:29+00:00 fe0d94f65bf2fcc6fea930360d834b199a77e1c2 When host PF writes the logical configuration for the GUC PAGING engine, the VF is meant to query it, and mirror it. Size of N means we have paging logical index range [0, N-1], with N fewer normal copy engines. Agreement is that PF will only spawn PAGING engines on NVL-S+, so this should be zero on older platforms, where we should simply fall back to the old behaviour. v2 (Sashiko): - We can't call use the guc_has_paging_engine() this early in the VF code. With that just unconditionally do the query, if the GuC is new enough and take the value as-is. With that drop the -1 special case and just let the upper layers figure out the rest. v3: - Also update xe_guc_klv_key_to_string. (Michal) - Add kernel-doc for xe_gt_sriov_vf_paging_engines(), plus other tweaks. (Michal) - Update with final GuC version. v4: - Just fallback to manual reserve when vf reported paging engines is zero. Will revisit in the future. v5 (Michal): - Convert the assert to a full abort if we ever see non-zero GuC paging engine count, on pre-nvl. - Move the VF hunk in guc_has_paging_engine() here. - Some small tweaks. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Piotr Piórkowski <piotr.piorkowski@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20260626111520.487997-20-matthew.auld@intel.com 
When host PF writes the logical configuration for the GUC PAGING engine,
the VF is meant to query it, and mirror it. Size of N means we have
paging logical index range [0, N-1], with N fewer normal copy engines.

Agreement is that PF will only spawn PAGING engines on NVL-S+, so this
should be zero on older platforms, where we should simply fall back to
the old behaviour.

v2 (Sashiko):
  - We can't call use the guc_has_paging_engine() this early in the VF
    code. With that just unconditionally do the query, if the GuC is new
    enough and take the value as-is. With that drop the -1 special case and
    just let the upper layers figure out the rest.
v3:
  - Also update xe_guc_klv_key_to_string. (Michal)
  - Add kernel-doc for xe_gt_sriov_vf_paging_engines(), plus other
    tweaks. (Michal)
  - Update with final GuC version.
v4:
  - Just fallback to manual reserve when vf reported paging engines is
    zero. Will revisit in the future.
v5 (Michal):
  - Convert the assert to a full abort if we ever see non-zero GuC
    paging engine count, on pre-nvl.
  - Move the VF hunk in guc_has_paging_engine() here.
  - Some small tweaks.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Piotr Piórkowski <piotr.piorkowski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patch.msgid.link/20260626111520.487997-20-matthew.auld@intel.com
drm/xe/guc: add the plumbing for GUC_PAGING_CLASS 2026-07-10T11:50:08+00:00 Matthew Auld matthew.auld@intel.com 2026-06-26T11:15:24+00:00 0c9a7926bd8edbeb6e416afdf07cfd8a96d56e20 On newer platforms, the GuC has a new engine class which we need to use to refer to the dedicated/reserved KMD BCS engine. With that, add the plumbing in the GuC backend to support GUC_PAGING_CLASS and GUC_CAPTURE_LIST_CLASS_PAGING. Currently this is still turned off. v2 (Daniele) - Also add adjust the capture list for hpg, so we account for nvl-s. - Move single paging engine assert to a more natural place. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patch.msgid.link/20260626111520.487997-15-matthew.auld@intel.com 
On newer platforms, the GuC has a new engine class which we need to use
to refer to the dedicated/reserved KMD BCS engine. With that, add the
plumbing in the GuC backend to support GUC_PAGING_CLASS and
GUC_CAPTURE_LIST_CLASS_PAGING.

Currently this is still turned off.

v2 (Daniele)
  - Also add adjust the capture list for hpg, so we account for nvl-s.
  - Move single paging engine assert to a more natural place.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patch.msgid.link/20260626111520.487997-15-matthew.auld@intel.com
drm/xe: Add support for WA 16029897822 2026-07-09T17:07:01+00:00 Daniele Ceraolo Spurio daniele.ceraolospurio@intel.com 2026-07-06T22:43:46+00:00 f543084cdbd142b9cfc1baf6f9d81e7b95fe9505 The WA is implemented by the GuC, so we just need to enable it via the dedicated KLV. This WA is supported starting from GuC 70.69. Note that the GuC does not enable the relevant feature on NVL-S, so this WA can't (and shouldn't) be enabled on that platform. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Julia Filipchuk <julia.filipchuk@intel.com> Link: https://patch.msgid.link/20260706224344.2723462-4-daniele.ceraolospurio@intel.com 
The WA is implemented by the GuC, so we just need to enable it via the
dedicated KLV.
This WA is supported starting from GuC 70.69. Note that the GuC does not
enable the relevant feature on NVL-S, so this WA can't (and shouldn't)
be enabled on that platform.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Julia Filipchuk <julia.filipchuk@intel.com>
Link: https://patch.msgid.link/20260706224344.2723462-4-daniele.ceraolospurio@intel.com
drm/xe: Add support for WA 22022079272 2026-07-09T17:07:01+00:00 Daniele Ceraolo Spurio daniele.ceraolospurio@intel.com 2026-07-06T22:43:45+00:00 0af278683cd61b6c31fbec7f548f89956f70c604 The WA is implemented by the GuC, so we just need to enable it via the dedicated KLV. This WA is supported starting from GuC 70.62. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patch.msgid.link/20260706224344.2723462-3-daniele.ceraolospurio@intel.com 
The WA is implemented by the GuC, so we just need to enable it via the
dedicated KLV.
This WA is supported starting from GuC 70.62.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patch.msgid.link/20260706224344.2723462-3-daniele.ceraolospurio@intel.com
drm/xe/guc: Handle GuC local uncorrectable error notifications 2026-07-09T17:03:12+00:00 Zhanjun Dong zhanjun.dong@intel.com 2026-07-06T23:43:53+00:00 4e57574fa3a3a152bcca40f7595a28e88af28b27 Add support for the GuC uncorrectable local error G2H notification and opt in to the feature when the submission ABI exposes it. When the notification targets a known exec queue, treat it like an engine reset request and route it through the existing timeout cleanup path. This keeps the queue teardown, pending job cancellation and error capture in one place instead of open-coding a parallel recovery flow. Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patch.msgid.link/20260706234353.3874355-1-zhanjun.dong@intel.com 
Add support for the GuC uncorrectable local error G2H notification and
opt in to the feature when the submission ABI exposes it.

When the notification targets a known exec queue, treat it like an
engine reset request and route it through the existing timeout cleanup
path. This keeps the queue teardown, pending job cancellation and error
capture in one place instead of open-coding a parallel recovery flow.

Signed-off-by: Zhanjun Dong <zhanjun.dong@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patch.msgid.link/20260706234353.3874355-1-zhanjun.dong@intel.com
drm/xe: Move xe_uc_fw_abi.h to abi/ 2026-05-27T19:28:01+00:00 Michal Wajdeczko michal.wajdeczko@intel.com 2026-05-27T11:26:07+00:00 637c8e3a525b73ac3cf765831119b02a927d11cd We aim to keep all pure ABI headers in the abi/ folder, but somehow we missed this file. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/20260527112608.22448-1-michal.wajdeczko@intel.com 
We aim to keep all pure ABI headers in the abi/ folder, but
somehow we missed this file.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/20260527112608.22448-1-michal.wajdeczko@intel.com
drm/xe/guc: Update POLICY_SCHED_IF_IDLE documentation 2026-04-12T08:32:43+00:00 Michal Wajdeczko michal.wajdeczko@intel.com 2026-04-02T19:17:14+00:00 3fb4d2c10702695f33eee9f00a94d2d5e91a5755 Starting from the GuC firmware version 70.12.0 the meaning of the POLICY_SCHED_IF_IDLE has changed, which now acts as a bulk update of the VF_CFG_SCHED_PRIORITY configurations of all VFs. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20260402191726.4932-2-michal.wajdeczko@intel.com 
Starting from the GuC firmware version 70.12.0 the meaning of the
POLICY_SCHED_IF_IDLE has changed, which now acts as a bulk update
of the VF_CFG_SCHED_PRIORITY configurations of all VFs.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Link: https://patch.msgid.link/20260402191726.4932-2-michal.wajdeczko@intel.com
drm/xe: Enable Wa_14025515070 2026-04-03T19:56:18+00:00 Julia Filipchuk julia.filipchuk@intel.com 2026-03-04T00:34:24+00:00 f9a21696e37b069c96b81fa0ad8392b7b6d4a47e Corrects a failure on context switch. On registration of context with indirect ring state will correct state of targeted and idle command streamers. This Wa requires GuC 70.53+ (uapi 1.26+). If indirect_ring_state is enabled and Wa is unavailable, notify and disable indirect_ring_state. Added additional XE_RTP_PASTE macros for expansion of longer rules. Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Julia Filipchuk <julia.filipchuk@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Link: https://patch.msgid.link/20260304003431.758201-4-julia.filipchuk@intel.com 
Corrects a failure on context switch. On registration of context with
indirect ring state will correct state of targeted and idle command
streamers.

This Wa requires GuC 70.53+ (uapi 1.26+).  If indirect_ring_state is
enabled and Wa is unavailable, notify and disable indirect_ring_state.

Added additional XE_RTP_PASTE macros for expansion of longer rules.

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Julia Filipchuk <julia.filipchuk@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Link: https://patch.msgid.link/20260304003431.758201-4-julia.filipchuk@intel.com