linux.git/drivers/gpu/drm/tegra/dp.c, branch v5.8 Linux kernel source tree drm/tegra: sor: Add DisplayPort support 2019-10-28T10:18:54+00:00 Thierry Reding treding@nvidia.com 2019-10-15T12:59:37+00:00 0472c21b83192c61dbac7ba98abe8decacbd1d59 Add support for regular DisplayPort on Tegra210 and Tegra186. Signed-off-by: Thierry Reding <treding@nvidia.com> 
Add support for regular DisplayPort on Tegra210 and Tegra186.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Add DisplayPort link training helper 2019-10-28T10:18:53+00:00 Thierry Reding treding@nvidia.com 2015-07-07T19:21:48+00:00 078c445733c1e8092e23391b251cad6b12f6156e Add a helper that will perform link training as described in the DisplayPort specification. Signed-off-by: Thierry Reding <treding@nvidia.com> 
Add a helper that will perform link training as described in the
DisplayPort specification.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Add support for eDP link rates 2019-10-28T10:18:53+00:00 Thierry Reding treding@nvidia.com 2018-02-01T16:46:42+00:00 6a127160c4883abf3a54d97024eda8118849fd5c Parses additional link rates from DPCD if the sink supports eDP 1.4. Signed-off-by: Thierry Reding <treding@nvidia.com> 
Parses additional link rates from DPCD if the sink supports eDP 1.4.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Add drm_dp_link_choose() helper 2019-10-28T10:18:52+00:00 Thierry Reding treding@nvidia.com 2015-07-21T14:38:11+00:00 01f09f242eb5cb194a88cef669a099fa10fcb3f0 This helper chooses an appropriate configuration, according to the bitrate requirements of the video mode and the capabilities of the DisplayPort sink. Signed-off-by: Thierry Reding <treding@nvidia.com> 
This helper chooses an appropriate configuration, according to the
bitrate requirements of the video mode and the capabilities of the
DisplayPort sink.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Enable alternate scrambler reset when supported 2019-10-28T10:18:52+00:00 Thierry Reding treding@nvidia.com 2015-07-07T19:14:12+00:00 c4a27288520d35e7e6acc6e36fba4585e1bddde6 If the sink is eDP and supports the alternate scrambler reset, enable it. Signed-off-by: Thierry Reding <treding@nvidia.com> 
If the sink is eDP and supports the alternate scrambler reset, enable
it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Set channel coding on link configuration 2019-10-28T10:18:52+00:00 Thierry Reding treding@nvidia.com 2015-06-10T14:35:44+00:00 553769ff8d8c452cc81a5fe5b0a68cc456c31db3 Make use of ANSI 8B/10B channel coding if the DisplayPort sink supports it. Signed-off-by: Thierry Reding <treding@nvidia.com> 
Make use of ANSI 8B/10B channel coding if the DisplayPort sink supports
it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Read AUX read interval from DPCD 2019-10-28T10:18:52+00:00 Thierry Reding treding@nvidia.com 2015-07-07T19:01:26+00:00 ad7f2dda38911698deb2cc9ea45362f9a127e3f4 Store the AUX read interval from DPCD, so that it can be used to wait for the durations given in the specification during link training. Signed-off-by: Thierry Reding <treding@nvidia.com> 
Store the AUX read interval from DPCD, so that it can be used to wait
for the durations given in the specification during link training.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Read eDP version from DPCD 2019-10-28T10:18:45+00:00 Thierry Reding treding@nvidia.com 2015-07-07T18:59:22+00:00 7aa3cc540d00b0be7d225202fa5c2d0c8e99f3f1 If the sink supports eDP, read the eDP revision from it's DPCD. Signed-off-by: Thierry Reding <treding@nvidia.com> 
If the sink supports eDP, read the eDP revision from it's DPCD.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Read alternate scrambler reset capability from sink 2019-10-28T10:18:45+00:00 Thierry Reding treding@nvidia.com 2018-02-05T14:16:18+00:00 4ff9ba5674d16857372b936a8d08920a9851d1cd Parse from the sink capabilities whether or not the eDP alternate scrambler reset value of 0xfffe is supported. Signed-off-by: Thierry Reding <treding@nvidia.com> 
Parse from the sink capabilities whether or not the eDP alternate
scrambler reset value of 0xfffe is supported.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Read channel coding capability from sink 2019-10-28T10:18:45+00:00 Thierry Reding treding@nvidia.com 2018-02-05T13:07:57+00:00 6c651b13e436030f996bcfb2f76833af94e44531 Parse from the sink capabilities whether or not it supports ANSI 8B/10B channel coding as specified in ANSI X3.230-1994, clause 11. Signed-off-by: Thierry Reding <treding@nvidia.com> 
Parse from the sink capabilities whether or not it supports ANSI 8B/10B
channel coding as specified in ANSI X3.230-1994, clause 11.

Signed-off-by: Thierry Reding <treding@nvidia.com>