linux.git/drivers/gpu/drm/msm, branch v4.1-rc2

Merge Linus master into drm-next

2015-04-20T03:05:20+00:00

The merge is clean, but the arm build fails afterwards,
due to API changes in the regulator tree.

I've included the patch into the merge to fix the build.

Signed-off-by: Dave Airlie

Merge remote-tracking branches 'regulator/topic/mode', 'regulator/topic/notifier', 'regulator/topic/palmas', 'regulator/topic/qcom' and 'regulator/topic/stw481x' into regulator-next

2015-04-10T18:16:03+00:00

drm/msm/mdp5: Enable DSI connector in msm drm driver

2015-04-01T23:29:38+00:00

This change adds the support in mdp5 kms driver for single
and dual DSI. Dual DSI case depends on the framework API
and sequence change to support dual data path.

v1: Initial change
v2: Address Rob Clark's comment
- Separate command mode encoder to a new file mdp5_cmd_encoder.c
- Rebase to not depend on msm_drm_sub_dev change

Signed-off-by: Hai Li 
Signed-off-by: Rob Clark

drm/msm: Initial add DSI connector support

2015-04-01T23:29:38+00:00

This change adds the DSI connector support in msm drm driver.

v1: Initial change
v2:
- Address comments from Archit + minor clean-ups
- Rebase to not depend on msm_drm_sub_dev change [Rob's comment]
v3: Fix issues when initialization is failed

Signed-off-by: Hai Li 
Signed-off-by: Rob Clark

drm/msm: Add split display interface

2015-04-01T23:29:37+00:00

This change is to add an interface to MDP for connector devices
setting split display information.

Signed-off-by: Hai Li 
Signed-off-by: Rob Clark

drm/msm/mdp5: Move *_modeset_init out of construct_encoder function

2015-04-01T23:29:37+00:00

This change is to make the content in construct_encoder reflect its
name.
Also, DSI connector may be connected to video mode or command mode
encoder, so that 2 different encoders need to be constructed for DSI.

Signed-off-by: Hai Li 
Signed-off-by: Rob Clark

drm/msm/mdp5: Remove CTL flush dummy bits

2015-04-01T23:29:37+00:00

This TODO can now be removed and replaced by the previous patch
"drm/msm/mdp5: Update headers (add CTL flush bits)"

Signed-off-by: Stephane Viau 
Signed-off-by: Rob Clark

drm/msm/mdp5: Update headers (add CTL flush bits)

2015-04-01T23:29:36+00:00

Some upcoming targets have more bits to set in CTL_FLUSH
registers.

Example: msm8x16 needs to set TIMING1 bit so that some of the
INTF1's interface registers get flushed.

Signed-off-by: Stephane Viau 
Signed-off-by: Rob Clark

drm/msm/mdp5: Add hardware configuration for msm8x16

2015-04-01T23:29:36+00:00

This change adds the hw configuration for msm8x16 chipsets in
mdp5_cfg module.

Note that only one external display interface is present in this
configuration (DSI) but has not been enabled yet. It will be enabled
once drm/msm driver supports DSI connectors.

v2: add CTL flush register's hardware mask [pointed by Archit]

Signed-off-by: Stephane Viau 
Signed-off-by: Rob Clark

drm/msm/mdp5: Get SMP client list from mdp5_cfg

2015-04-01T23:29:36+00:00

SMP blocks are configured for specific client IDs (ports).
These client IDs can be different from one chip to another for a
given pipe.

e.g.: DMA0 pipe fetch Y component is connected to:
 - port #10 for MDP5 v1.3
 - port #4 for MDP5 v1.6

In order to be compatible for upcoming versions of MDP5, the
client ID list is passed through the MDP5 config module rather
than using a list of hard-coded enum values.

Signed-off-by: Stephane Viau 
Signed-off-by: Rob Clark