<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/gpu/drm/imagination, branch v6.16</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>drm/imagination: Fix kernel crash when hard resetting the GPU</title>
<updated>2025-07-04T15:32:10+00:00</updated>
<author>
<name>Alessio Belle</name>
<email>alessio.belle@imgtec.com</email>
</author>
<published>2025-06-24T14:22:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=d38376b3ee48d073c64e75e150510d7e6b4b04f7'/>
<id>d38376b3ee48d073c64e75e150510d7e6b4b04f7</id>
<content type='text'>
The GPU hard reset sequence calls pm_runtime_force_suspend() and
pm_runtime_force_resume(), which according to their documentation should
only be used during system-wide PM transitions to sleep states.

The main issue though is that depending on some internal runtime PM
state as seen by pm_runtime_force_suspend() (whether the usage count is
&lt;= 1), pm_runtime_force_resume() might not resume the device unless
needed. If that happens, the runtime PM resume callback
pvr_power_device_resume() is not called, the GPU clocks are not
re-enabled, and the kernel crashes on the next attempt to access GPU
registers as part of the power-on sequence.

Replace calls to pm_runtime_force_suspend() and
pm_runtime_force_resume() with direct calls to the driver's runtime PM
callbacks, pvr_power_device_suspend() and pvr_power_device_resume(),
to ensure clocks are re-enabled and avoid the kernel crash.

Fixes: cc1aeedb98ad ("drm/imagination: Implement firmware infrastructure and META FW support")
Signed-off-by: Alessio Belle &lt;alessio.belle@imgtec.com&gt;
Reviewed-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250624-fix-kernel-crash-gpu-hard-reset-v1-1-6d24810d72a6@imgtec.com
Cc: stable@vger.kernel.org
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The GPU hard reset sequence calls pm_runtime_force_suspend() and
pm_runtime_force_resume(), which according to their documentation should
only be used during system-wide PM transitions to sleep states.

The main issue though is that depending on some internal runtime PM
state as seen by pm_runtime_force_suspend() (whether the usage count is
&lt;= 1), pm_runtime_force_resume() might not resume the device unless
needed. If that happens, the runtime PM resume callback
pvr_power_device_resume() is not called, the GPU clocks are not
re-enabled, and the kernel crashes on the next attempt to access GPU
registers as part of the power-on sequence.

Replace calls to pm_runtime_force_suspend() and
pm_runtime_force_resume() with direct calls to the driver's runtime PM
callbacks, pvr_power_device_suspend() and pvr_power_device_resume(),
to ensure clocks are re-enabled and avoid the kernel crash.

Fixes: cc1aeedb98ad ("drm/imagination: Implement firmware infrastructure and META FW support")
Signed-off-by: Alessio Belle &lt;alessio.belle@imgtec.com&gt;
Reviewed-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250624-fix-kernel-crash-gpu-hard-reset-v1-1-6d24810d72a6@imgtec.com
Cc: stable@vger.kernel.org
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/imagination: Add reset controller support for GPU initialization</title>
<updated>2025-04-24T10:08:48+00:00</updated>
<author>
<name>Michal Wilczynski</name>
<email>m.wilczynski@samsung.com</email>
</author>
<published>2025-04-18T11:22:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=3a2b7389feea9a7afd18d58cda59b7a989445f38'/>
<id>3a2b7389feea9a7afd18d58cda59b7a989445f38</id>
<content type='text'>
All IMG Rogue GPUs include a reset line that participates in the
power-up sequence. On some SoCs (e.g., T-Head TH1520 and Banana Pi
BPI-F3), this reset line is exposed and must be driven explicitly to
ensure proper initialization.  On others, such as the currently
supported TI SoC, the reset logic is handled in hardware or firmware
without exposing the line directly. In platforms where the reset line is
externally accessible, if it is not driven correctly, the GPU may remain
in an undefined state, leading to instability or performance issues.

This commit adds a dedicated reset controller to the drm/imagination
driver.  By managing the reset line (where applicable) as part of normal
GPU bring-up, the driver ensures reliable initialization across
platforms regardless of whether the reset is controlled externally or
handled internally.

Signed-off-by: Michal Wilczynski &lt;m.wilczynski@samsung.com&gt;
Reviewed-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250418-apr_18_reset_img-v6-2-85a06757b698@samsung.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
All IMG Rogue GPUs include a reset line that participates in the
power-up sequence. On some SoCs (e.g., T-Head TH1520 and Banana Pi
BPI-F3), this reset line is exposed and must be driven explicitly to
ensure proper initialization.  On others, such as the currently
supported TI SoC, the reset logic is handled in hardware or firmware
without exposing the line directly. In platforms where the reset line is
externally accessible, if it is not driven correctly, the GPU may remain
in an undefined state, leading to instability or performance issues.

This commit adds a dedicated reset controller to the drm/imagination
driver.  By managing the reset line (where applicable) as part of normal
GPU bring-up, the driver ensures reliable initialization across
platforms regardless of whether the reset is controlled externally or
handled internally.

Signed-off-by: Michal Wilczynski &lt;m.wilczynski@samsung.com&gt;
Reviewed-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250418-apr_18_reset_img-v6-2-85a06757b698@samsung.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/imagination: avoid unused-const-variable warning</title>
<updated>2025-04-24T09:51:55+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2025-04-09T12:22:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=3206a96675342badb0254558ba4b4c8764aa3ae7'/>
<id>3206a96675342badb0254558ba4b4c8764aa3ae7</id>
<content type='text'>
When CONFIG_DEBUG_FS is disabled, the stid_fmts[] array is not referenced
anywhere, causing a W=1 warning with gcc:

In file included from drivers/gpu/drm/imagination/pvr_fw_trace.c:7:
drivers/gpu/drm/imagination/pvr_rogue_fwif_sf.h:75:39: error: 'stid_fmts' defined but not used [-Werror=unused-const-variable=]
   75 | static const struct rogue_km_stid_fmt stid_fmts[] = {
      |                                       ^~~~~~~~~

Rather than adding more #ifdef blocks, address this by changing the
existing #ifdef into equivalent IS_ENABLED() checks so gcc can see
where the symbol is used but still eliminate it from the object file.

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Reviewed-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250409122314.2848028-1-arnd@kernel.org
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When CONFIG_DEBUG_FS is disabled, the stid_fmts[] array is not referenced
anywhere, causing a W=1 warning with gcc:

In file included from drivers/gpu/drm/imagination/pvr_fw_trace.c:7:
drivers/gpu/drm/imagination/pvr_rogue_fwif_sf.h:75:39: error: 'stid_fmts' defined but not used [-Werror=unused-const-variable=]
   75 | static const struct rogue_km_stid_fmt stid_fmts[] = {
      |                                       ^~~~~~~~~

Rather than adding more #ifdef blocks, address this by changing the
existing #ifdef into equivalent IS_ENABLED() checks so gcc can see
where the symbol is used but still eliminate it from the object file.

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Reviewed-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250409122314.2848028-1-arnd@kernel.org
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/imagination: Add support for TI AM68 GPU</title>
<updated>2025-04-15T11:21:52+00:00</updated>
<author>
<name>Matt Coster</name>
<email>matt.coster@imgtec.com</email>
</author>
<published>2025-04-10T09:55:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=81f6e0e0f3505809dd78eab129106f1c0cf2baf1'/>
<id>81f6e0e0f3505809dd78eab129106f1c0cf2baf1</id>
<content type='text'>
Since we already added a generic compatible string for all IMG Rogue GPUs
("img,img-rogue"), all that's needed here is to link the appropriate
firmware for the BXS-4-64 GPU in the AM68.

Reviewed-by: Frank Binns &lt;frank.binns@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-16-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Since we already added a generic compatible string for all IMG Rogue GPUs
("img,img-rogue"), all that's needed here is to link the appropriate
firmware for the BXS-4-64 GPU in the AM68.

Reviewed-by: Frank Binns &lt;frank.binns@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-16-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/imagination: Use cached memory with dma_coherent</title>
<updated>2025-04-15T11:21:52+00:00</updated>
<author>
<name>Matt Coster</name>
<email>matt.coster@imgtec.com</email>
</author>
<published>2025-04-10T09:55:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=f0a1ab65d90420f2817569bbf67111feb8e6821e'/>
<id>f0a1ab65d90420f2817569bbf67111feb8e6821e</id>
<content type='text'>
The TI k3-j721s2 platform does not allow us to use uncached memory
(which is what the driver currently does) without disabling cache snooping
on the AXI ACE-Lite interface, which would be too much of a performance
hit.

Given the platform is dma-coherent, we can simply force all
device-accessible memory allocations through the CPU cache. In fact, this
can be done whenever the dma_coherent attribute is present.

Reviewed-by: Frank Binns &lt;frank.binns@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-15-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The TI k3-j721s2 platform does not allow us to use uncached memory
(which is what the driver currently does) without disabling cache snooping
on the AXI ACE-Lite interface, which would be too much of a performance
hit.

Given the platform is dma-coherent, we can simply force all
device-accessible memory allocations through the CPU cache. In fact, this
can be done whenever the dma_coherent attribute is present.

Reviewed-by: Frank Binns &lt;frank.binns@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-15-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/imagination: Add RISC-V firmware processor support</title>
<updated>2025-04-15T11:21:52+00:00</updated>
<author>
<name>Sarah Walker</name>
<email>sarah.walker@imgtec.com</email>
</author>
<published>2025-04-10T09:55:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=171f378d2a23db92d3443173f5fd7f25633ec39d'/>
<id>171f378d2a23db92d3443173f5fd7f25633ec39d</id>
<content type='text'>
Newer PowerVR GPUs (such as the BXS-4-64 MC1) use a RISC-V firmware
processor instead of the previous MIPS or META.

The current version of this patch depends on a patch[1] which exists in
drm-misc-fixes, but has not yet made it back to drm-misc-next (the
target of this patch). That patch adds the function pvr_vm_unmap_obj()
which is used here.

[1]: https://lore.kernel.org/r/20250226-hold-drm_gem_gpuva-lock-for-unmap-v2-1-3fdacded227f@imgtec.com

Signed-off-by: Sarah Walker &lt;sarah.walker@imgtec.com&gt;
Reviewed-by: Frank Binns &lt;frank.binns@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-14-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Newer PowerVR GPUs (such as the BXS-4-64 MC1) use a RISC-V firmware
processor instead of the previous MIPS or META.

The current version of this patch depends on a patch[1] which exists in
drm-misc-fixes, but has not yet made it back to drm-misc-next (the
target of this patch). That patch adds the function pvr_vm_unmap_obj()
which is used here.

[1]: https://lore.kernel.org/r/20250226-hold-drm_gem_gpuva-lock-for-unmap-v2-1-3fdacded227f@imgtec.com

Signed-off-by: Sarah Walker &lt;sarah.walker@imgtec.com&gt;
Reviewed-by: Frank Binns &lt;frank.binns@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-14-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/imagination: Move ELF fw utils to common file</title>
<updated>2025-04-15T11:21:52+00:00</updated>
<author>
<name>Matt Coster</name>
<email>matt.coster@imgtec.com</email>
</author>
<published>2025-04-10T09:55:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=f48485ab506850b4e35ff56550568f710a22a586'/>
<id>f48485ab506850b4e35ff56550568f710a22a586</id>
<content type='text'>
Currently only MIPS firmware processors use ELF-formatted firmware. When
adding support for RISC-V firmware processors, it will be useful to have
ELF handling functions ready to go.

Reviewed-by: Frank Binns &lt;frank.binns@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-13-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Currently only MIPS firmware processors use ELF-formatted firmware. When
adding support for RISC-V firmware processors, it will be useful to have
ELF handling functions ready to go.

Reviewed-by: Frank Binns &lt;frank.binns@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-13-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/imagination: Use callbacks for fw irq handling</title>
<updated>2025-04-15T11:21:51+00:00</updated>
<author>
<name>Matt Coster</name>
<email>matt.coster@imgtec.com</email>
</author>
<published>2025-04-10T09:55:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=89b3c4a5cc1b95f09f5fa5c183aa9d7a65309eac'/>
<id>89b3c4a5cc1b95f09f5fa5c183aa9d7a65309eac</id>
<content type='text'>
This allows for more versatility in checking and clearing firmware
registers used for interrupt handling.

Reviewed-by: Frank Binns &lt;frank.binns@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-12-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This allows for more versatility in checking and clearing firmware
registers used for interrupt handling.

Reviewed-by: Frank Binns &lt;frank.binns@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-12-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/imagination: Use a lookup table for fw defs</title>
<updated>2025-04-15T11:21:51+00:00</updated>
<author>
<name>Matt Coster</name>
<email>matt.coster@imgtec.com</email>
</author>
<published>2025-04-10T09:55:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=544b9b3b6fbd28473df9be42c815b2a5d97ae37b'/>
<id>544b9b3b6fbd28473df9be42c815b2a5d97ae37b</id>
<content type='text'>
With more than two firmware processor types, the if/else chain in
pvr_fw_init() gets a bit ridiculous. Use a static array indexed on
pvr_fw_processor_type (which is now a proper enum instead of #defines)
instead.

Reviewed-by: Frank Binns &lt;frank.binns@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-11-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
With more than two firmware processor types, the if/else chain in
pvr_fw_init() gets a bit ridiculous. Use a static array indexed on
pvr_fw_processor_type (which is now a proper enum instead of #defines)
instead.

Reviewed-by: Frank Binns &lt;frank.binns@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-11-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/imagination: Make has_fixed_data_addr a value</title>
<updated>2025-04-15T11:21:51+00:00</updated>
<author>
<name>Matt Coster</name>
<email>matt.coster@imgtec.com</email>
</author>
<published>2025-04-10T09:55:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=28dbcfbc01f32ac9c7c5c5f7b3a12c8cf701a989'/>
<id>28dbcfbc01f32ac9c7c5c5f7b3a12c8cf701a989</id>
<content type='text'>
This is currently a callback function which takes no parameters; there's
no reason for this so let's make it a straightforward value in pvr_fw_defs.

Reviewed-by: Frank Binns &lt;frank.binns@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-10-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This is currently a callback function which takes no parameters; there's
no reason for this so let's make it a straightforward value in pvr_fw_defs.

Reviewed-by: Frank Binns &lt;frank.binns@imgtec.com&gt;
Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-10-eda620c5865f@imgtec.com
Signed-off-by: Matt Coster &lt;matt.coster@imgtec.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
