<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/gpu/drm/amd, branch v6.5-rc2</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>Merge tag 'amd-drm-fixes-6.5-2023-07-12' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes</title>
<updated>2023-07-14T03:19:54+00:00</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2023-07-14T01:44:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=38d88d5e97c9032ebeca092b9372209f2ca92cdf'/>
<id>38d88d5e97c9032ebeca092b9372209f2ca92cdf</id>
<content type='text'>
amd-drm-fixes-6.5-2023-07-12:

amdgpu:
- SMU i2c locking fix
- Fix a possible deadlock in process restoration for ROCm apps
- Disable PCIe lane/speed switching on Intel platforms (the platforms don't support it)

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;

From: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20230712184009.7740-1-alexander.deucher@amd.com
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
amd-drm-fixes-6.5-2023-07-12:

amdgpu:
- SMU i2c locking fix
- Fix a possible deadlock in process restoration for ROCm apps
- Disable PCIe lane/speed switching on Intel platforms (the platforms don't support it)

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;

From: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20230712184009.7740-1-alexander.deucher@amd.com
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd: Align SMU11 SMU_MSG_OverridePcieParameters implementation with SMU13</title>
<updated>2023-07-12T16:21:23+00:00</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2023-07-08T02:26:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=e701156ccc6c7a5f104a968dda74cd6434178712'/>
<id>e701156ccc6c7a5f104a968dda74cd6434178712</id>
<content type='text'>
SMU13 overrides dynamic PCIe lane width and dynamic speed by when on
certain hosts. commit 38e4ced80479 ("drm/amd/pm: conditionally disable
pcie lane switching for some sienna_cichlid SKUs") worked around this
issue by setting up certain SKUs to set up certain limits, but the same
fundamental problem with those hosts affects all SMU11 implmentations
as well, so align the SMU11 and SMU13 driver handling.

Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
SMU13 overrides dynamic PCIe lane width and dynamic speed by when on
certain hosts. commit 38e4ced80479 ("drm/amd/pm: conditionally disable
pcie lane switching for some sienna_cichlid SKUs") worked around this
issue by setting up certain SKUs to set up certain limits, but the same
fundamental problem with those hosts affects all SMU11 implmentations
as well, so align the SMU11 and SMU13 driver handling.

Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd: Move helper for dynamic speed switch check out of smu13</title>
<updated>2023-07-12T16:09:54+00:00</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2023-07-08T02:26:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=188623076d0f1a500583d392b6187056bf7cc71a'/>
<id>188623076d0f1a500583d392b6187056bf7cc71a</id>
<content type='text'>
This helper is used for checking if the connected host supports
the feature, it can be moved into generic code to be used by other
smu implementations as well.

Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This helper is used for checking if the connected host supports
the feature, it can be moved into generic code to be used by other
smu implementations as well.

Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/pm: conditionally disable pcie lane/speed switching for SMU13</title>
<updated>2023-07-12T16:08:17+00:00</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2023-07-07T19:31:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=31c7a3b378a136adc63296a2ff17645896fcf303'/>
<id>31c7a3b378a136adc63296a2ff17645896fcf303</id>
<content type='text'>
Intel platforms such as Sapphire Rapids and Raptor Lake don't support
dynamic pcie lane or speed switching.

This limitation seems to carry over from one generation to another.
To be safer, disable dynamic pcie lane width and speed switching when
running on an Intel platform.

Link: https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2663
Co-developed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Intel platforms such as Sapphire Rapids and Raptor Lake don't support
dynamic pcie lane or speed switching.

This limitation seems to carry over from one generation to another.
To be safer, disable dynamic pcie lane width and speed switching when
running on an Intel platform.

Link: https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2663
Co-developed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/pm: share the code around SMU13 pcie parameters update</title>
<updated>2023-07-12T16:07:43+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2023-07-07T19:31:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=dcb489bae65d92cfd26da22c7a0d6665b06ecc63'/>
<id>dcb489bae65d92cfd26da22c7a0d6665b06ecc63</id>
<content type='text'>
So that SMU13.0.0 and SMU13.0.7 do not need to have one copy each.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
So that SMU13.0.0 and SMU13.0.7 do not need to have one copy each.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amdgpu: avoid restore process run into dead loop.</title>
<updated>2023-07-12T16:07:13+00:00</updated>
<author>
<name>gaba</name>
<email>gaba@amd.com</email>
</author>
<published>2023-03-03T00:03:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=8a774fe912ff09e39c2d3a3589c729330113f388'/>
<id>8a774fe912ff09e39c2d3a3589c729330113f388</id>
<content type='text'>
In restore process worker, pinned BO cause update PTE fail, then
the function re-schedule the restore_work. This will generate dead loop.

Signed-off-by: gaba &lt;gaba@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In restore process worker, pinned BO cause update PTE fail, then
the function re-schedule the restore_work. This will generate dead loop.

Signed-off-by: gaba &lt;gaba@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/pm: fix smu i2c data read risk</title>
<updated>2023-07-12T16:06:16+00:00</updated>
<author>
<name>Yang Wang</name>
<email>kevinyang.wang@amd.com</email>
</author>
<published>2023-06-20T09:05:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=d934e537c14bfe1227ced6341472571f354383e8'/>
<id>d934e537c14bfe1227ced6341472571f354383e8</id>
<content type='text'>
the smu driver_table is used for all types of smu
tables data transcation (e.g: PPtable, Metrics, i2c, Ecc..).

it is necessary to hold this lock to avoiding data tampering
during the i2c read operation.

Signed-off-by: Yang Wang &lt;kevinyang.wang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
the smu driver_table is used for all types of smu
tables data transcation (e.g: PPtable, Metrics, i2c, Ecc..).

it is necessary to hold this lock to avoiding data tampering
during the i2c read operation.

Signed-off-by: Yang Wang &lt;kevinyang.wang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'drm-next-2023-07-07' of git://anongit.freedesktop.org/drm/drm</title>
<updated>2023-07-07T05:42:54+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2023-07-07T05:42:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=5133c9e51de41bfa902153888e11add3342ede18'/>
<id>5133c9e51de41bfa902153888e11add3342ede18</id>
<content type='text'>
Pull drm fixes from Dave Airlie:
 "Lots of fixes, mostly i915 and amdgpu. It's two weeks of i915, and I
  think three weeks of amdgpu.

  fbdev:
   - Fix module infos on sparc

  panel:
   - Fix mode on Starry-ili9882t

  i915:
   - Allow DC states along with PW2 only for PWB functionality [adlp+]
   - Fix SSC selection for MPLLA [mtl]
   - Use hw.adjusted mode when calculating io/fast wake times [psr]
   - Apply min softlimit correctly [guc/slpc]
   - Assign correct hdcp content type [hdcp]
   - Add missing forward declarations/includes to display power headers
   - Fix BDW PSR AUX CH data register offsets [psr]
   - Use mock device info for creating mock device

  amdgpu:
   - Misc cleanups
   - GFX 9.4.3 fixes
   - DEBUGFS build fix
   - Fix LPDDR5 reporting
   - ASPM fixes
   - DCN 3.1.4 fixes
   - DP MST fixes
   - DCN 3.2.x fixes
   - Display PSR TCON fixes
   - SMU 13.x fixes
   - RAS fixes
   - Vega12/20 SMU fixes
   - PSP flashing cleanup
   - GFX9 MCBP fixes
   - SR-IOV fixes
   - GPUVM clear mappings fix for always valid BOs
   - Add FAMS quirk for problematic monitor
   - Fix possible UAF
   - Better handle monentary temperature fluctuations
   - SDMA 4.4.2 fixes
   - Fencing fix"

* tag 'drm-next-2023-07-07' of git://anongit.freedesktop.org/drm/drm: (83 commits)
  drm/i915: use mock device info for creating mock device
  drm/i915/psr: Fix BDW PSR AUX CH data register offsets
  drm/amdgpu: Fix potential fence use-after-free v2
  drm/amd/pm: avoid unintentional shutdown due to temperature momentary fluctuation
  drm/amd/pm: expose swctf threshold setting for legacy powerplay
  drm/amd/display: 3.2.241
  drm/amd/display: Take full update path if number of planes changed
  drm/amd/display: Create debugging mechanism for Gaming FAMS
  drm/amd/display: Add monitor specific edid quirk
  drm/amd/display: For new fast update path, loop through each surface
  drm/amd/display: Remove Phantom Pipe Check When Calculating K1 and K2
  drm/amd/display: Limit new fast update path to addr and gamma / color
  drm/amd/display: Fix the delta clamping for shaper LUT
  drm/amdgpu: Keep non-psp path for partition switch
  drm/amd/display: program DPP shaper and 3D LUT if updated
  Revert "drm/amd/display: edp do not add non-edid timings"
  drm/amdgpu: share drm device for pci amdgpu device with 1st partition device
  drm/amd/pm: Add GFX v9.4.3 unique id to sysfs
  drm/amd/pm: Enable pp_feature attribute
  drm/amdgpu/vcn: Need to unpause dpg before stop dpg
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull drm fixes from Dave Airlie:
 "Lots of fixes, mostly i915 and amdgpu. It's two weeks of i915, and I
  think three weeks of amdgpu.

  fbdev:
   - Fix module infos on sparc

  panel:
   - Fix mode on Starry-ili9882t

  i915:
   - Allow DC states along with PW2 only for PWB functionality [adlp+]
   - Fix SSC selection for MPLLA [mtl]
   - Use hw.adjusted mode when calculating io/fast wake times [psr]
   - Apply min softlimit correctly [guc/slpc]
   - Assign correct hdcp content type [hdcp]
   - Add missing forward declarations/includes to display power headers
   - Fix BDW PSR AUX CH data register offsets [psr]
   - Use mock device info for creating mock device

  amdgpu:
   - Misc cleanups
   - GFX 9.4.3 fixes
   - DEBUGFS build fix
   - Fix LPDDR5 reporting
   - ASPM fixes
   - DCN 3.1.4 fixes
   - DP MST fixes
   - DCN 3.2.x fixes
   - Display PSR TCON fixes
   - SMU 13.x fixes
   - RAS fixes
   - Vega12/20 SMU fixes
   - PSP flashing cleanup
   - GFX9 MCBP fixes
   - SR-IOV fixes
   - GPUVM clear mappings fix for always valid BOs
   - Add FAMS quirk for problematic monitor
   - Fix possible UAF
   - Better handle monentary temperature fluctuations
   - SDMA 4.4.2 fixes
   - Fencing fix"

* tag 'drm-next-2023-07-07' of git://anongit.freedesktop.org/drm/drm: (83 commits)
  drm/i915: use mock device info for creating mock device
  drm/i915/psr: Fix BDW PSR AUX CH data register offsets
  drm/amdgpu: Fix potential fence use-after-free v2
  drm/amd/pm: avoid unintentional shutdown due to temperature momentary fluctuation
  drm/amd/pm: expose swctf threshold setting for legacy powerplay
  drm/amd/display: 3.2.241
  drm/amd/display: Take full update path if number of planes changed
  drm/amd/display: Create debugging mechanism for Gaming FAMS
  drm/amd/display: Add monitor specific edid quirk
  drm/amd/display: For new fast update path, loop through each surface
  drm/amd/display: Remove Phantom Pipe Check When Calculating K1 and K2
  drm/amd/display: Limit new fast update path to addr and gamma / color
  drm/amd/display: Fix the delta clamping for shaper LUT
  drm/amdgpu: Keep non-psp path for partition switch
  drm/amd/display: program DPP shaper and 3D LUT if updated
  Revert "drm/amd/display: edp do not add non-edid timings"
  drm/amdgpu: share drm device for pci amdgpu device with 1st partition device
  drm/amd/pm: Add GFX v9.4.3 unique id to sysfs
  drm/amd/pm: Enable pp_feature attribute
  drm/amdgpu/vcn: Need to unpause dpg before stop dpg
  ...
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix potential fence use-after-free v2</title>
<updated>2023-06-30T17:12:16+00:00</updated>
<author>
<name>shanzhulig</name>
<email>shanzhulig@gmail.com</email>
</author>
<published>2023-06-28T01:10:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=2e54154b9f27262efd0cb4f903cc7d5ad1fe9628'/>
<id>2e54154b9f27262efd0cb4f903cc7d5ad1fe9628</id>
<content type='text'>
fence Decrements the reference count before exiting.
Avoid Race Vulnerabilities for fence use-after-free.

v2 (chk): actually fix the use after free and not just move it.

Signed-off-by: shanzhulig &lt;shanzhulig@gmail.com&gt;
Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
fence Decrements the reference count before exiting.
Avoid Race Vulnerabilities for fence use-after-free.

v2 (chk): actually fix the use after free and not just move it.

Signed-off-by: shanzhulig &lt;shanzhulig@gmail.com&gt;
Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/pm: avoid unintentional shutdown due to temperature momentary fluctuation</title>
<updated>2023-06-30T17:12:16+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2023-05-04T09:09:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=b75efe88b20c2be28b67e2821a794cc183e32374'/>
<id>b75efe88b20c2be28b67e2821a794cc183e32374</id>
<content type='text'>
An intentional delay is added on soft ctf triggered. Then there will
be a double check for the GPU temperature before taking further
action. This can avoid unintended shutdown due to temperature
momentary fluctuation.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
An intentional delay is added on soft ctf triggered. Then there will
be a double check for the GPU temperature before taking further
action. This can avoid unintended shutdown due to temperature
momentary fluctuation.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
