linux.git/drivers/gpu/drm/amd, branch v6.3-rc5

drm/amdgpu: allow more APUs to do mode2 reset when go to S4

2023-03-30T15:23:58+00:00

Skip mode2 reset only for IMU enabled APUs when do S4.

This patch is to fix the regression issue
https://gitlab.freedesktop.org/drm/amd/-/issues/2483
It is generated by commit b589626674de ("drm/amdgpu: skip ASIC reset
for APUs when go to S4").

Fixes: b589626674de ("drm/amdgpu: skip ASIC reset for APUs when go to S4")
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2483
Tested-by:  Yuan  Perry 
Signed-off-by: Tim Huang 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org # 6.1.x

drm/amd/display: Take FEC Overhead into Timeslot Calculation

2023-03-29T21:21:06+00:00

8b/10b encoding needs to add 3% fec overhead into the pbn.
In the Synapcis Cascaded MST hub, the first stage MST branch device
needs the information to determine the timeslot count for the
second stage MST branch device. Missing this overhead will leads to
insufficient timeslot allocation.

Cc: stable@vger.kernel.org
Cc: Mario Limonciello 
Reviewed-by: Hersen Wu 
Acked-by: Qingqing Zhuo 
Signed-off-by: Fangzhi Zuo 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Add DSC Support for Synaptics Cascaded MST Hub

2023-03-29T21:21:05+00:00

Traditional synaptics hub has one MST branch device without virtual dpcd.
Synaptics cascaded hub has two chained MST branch devices. DSC decoding
is performed via root MST branch device, instead of the second MST branch
device.

Reviewed-by: Hersen Wu 
Acked-by: Qingqing Zhuo 
Signed-off-by: Fangzhi Zuo 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org

drm/amd/display: Set dcn32 caps.seamless_odm

2023-03-23T13:39:34+00:00

[Why & How]
seamless_odm set was not picked up while
merging commit 2d017189e2b3 ("drm/amd/display:
Blank eDP on enable drv if odm enabled")

Fixes: 2d017189e2b3 ("drm/amd/display: Blank eDP on enable drv if odm enabled")
Reviewed-by: Qingqing Zhuo 
Acked-by: Qingqing Zhuo 
Signed-off-by: Hersen Wu 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: fix wrong index used in dccg32_set_dpstreamclk

2023-03-23T13:39:34+00:00

[Why & How]
When merging commit 9af611f29034
("drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming"),
index change was not picked up.

Cc: stable@vger.kernel.org
Cc: Mario Limonciello 
Fixes: 9af611f29034 ("drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming")
Reviewed-by: Qingqing Zhuo 
Acked-by: Qingqing Zhuo 
Signed-off-by: Hersen Wu 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amdgpu/nv: Apply ASPM quirk on Intel ADL + AMD Navi

2023-03-23T13:34:35+00:00

S2idle resume freeze can be observed on Intel ADL + AMD WX5500. This is
caused by commit 0064b0ce85bb ("drm/amd/pm: enable ASPM by default").

The root cause is still not clear for now.

So extend and apply the ASPM quirk from commit e02fe3bc7aba
("drm/amdgpu: vi: disable ASPM on Intel Alder Lake based systems"), to
workaround the issue on Navi cards too.

Fixes: 0064b0ce85bb ("drm/amd/pm: enable ASPM by default")
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2458
Reviewed-by: Alex Deucher 
Signed-off-by: Kai-Heng Feng 
Reviewed-by: Mario Limonciello 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org

drm/amd/display: remove outdated 8bpc comments

2023-03-23T13:34:07+00:00

[Why]
The commit c76e483cd916 ("drm/amd/display: Don't restrict bpc to 8 bpc")
removes the historical 8bpc dependency and sets max_bpc to 16.

[How]
The comment that states "8bpc for non-edp" needs to be removed as well.

Reviewed-by: Harry Wentland 
Acked-by: Qingqing Zhuo 
Signed-off-by: Alex Hung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amdgpu/gfx: set cg flags to enter/exit safe mode

2023-03-23T13:32:01+00:00

sriov needs to enter/exit safe mode in update umd p state
add the cg flag to let it enter or exit while needed

Signed-off-by: Jane Jian 
Reviewed-by: Lijo Lazar 
Signed-off-by: Alex Deucher

drm/amdgpu: Force signal hw_fences that are embedded in non-sched jobs

2023-03-23T13:31:30+00:00

[Why]
For engines not supporting soft reset, i.e. VCN, there will be a failed
ib test before mode 1 reset during asic reset. The fences in this case
are never signaled and next time when we try to free the sa_bo, kernel
will hang.

[How]
During pre_asic_reset, driver will clear job fences and afterwards the
fences' refcount will be reduced to 1. For drm_sched_jobs it will be
released in job_free_cb, and for non-sched jobs like ib_test, it's meant
to be released in sa_bo_free but only when the fences are signaled. So
we have to force signal the non_sched bad job's fence during
pre_asic_reset or the clear is not complete.

Signed-off-by: YuBiao Wang 
Acked-by: Luben Tuikov 
Signed-off-by: Alex Deucher

drm/amdgpu: add mes resume when do gfx post soft reset

2023-03-23T13:30:59+00:00

[why]
when gfx do soft reset, mes will also do reset, if mes is not
resumed when do recover from soft reset, mes is unable to respond
in later sequence

[how]
resume mes when do gfx post soft reset

Signed-off-by: Tong Liu01 
Acked-by: Alex Deucher 
Signed-off-by: Alex Deucher