linux.git/drivers/gpu/drm/amd, branch v5.7-rc4

drm/amd/display: Use cursor locking to prevent flip delays

2020-04-28T20:45:14+00:00

[Why]
Current locking scheme for cursor can result in a flip missing
its vsync, deferring it for one or more vsyncs.  Result is a
potential for stuttering when cursor is moved.

[How]
Use cursor update lock so that flips are not blocked while cursor
is being programmed.

Signed-off-by: Aric Cyr 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher

drm/amd/display: Update downspread percent to match spreadsheet for DCN2.1

2020-04-28T20:44:36+00:00

[WHY]
The downspread percentage was copied over from a previous version
of the display_mode_lib spreadsheet. This value has been updated,
and the previous value is too high to allow for such modes as
4K120hz. The new value is sufficient for such modes.

[HOW]
Update the value in dcn21_resource to match the spreadsheet.

Signed-off-by: Sung Lee 
Reviewed-by: Yongqiang Sun 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher

drm/amd/display: Defer cursor update around VUPDATE for all ASIC

2020-04-28T20:44:13+00:00

[Why]
Fixes the following scenario:

- Flip has been prepared sometime during the frame, update pending
- Cursor update happens right when VUPDATE would happen
- OPTC lock acquired, VUPDATE is blocked until next frame
- Flip is delayed potentially infinitely

With the igt@kms_cursor_legacy cursor-vs-flip-legacy test we can
observe nearly *13* frames of delay for some flips on Navi.

[How]
Apply the Raven workaround generically. When close enough to VUPDATE
block cursor updates from occurring from the dc_stream_set_cursor_*
helpers.

This could perhaps be a little smarter by checking if there were
pending updates or flips earlier in the frame on the HUBP side before
applying the delay, but this should be fine for now.

This fixes the kms_cursor_legacy test.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Aric Cyr 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher

drm/amd/display: fix rn soc bb update

2020-04-28T20:43:13+00:00

Currently RN SOC bounding box update assumes we will get at least
2 clock states from SMU. This isn't always true and because of special
casing on first clock state we end up with low disp, dpp, dsc and phy
clocks.

This change removes the special casing allowing the first state to
acquire correct clocks.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Yang 
Acked-by: Aurabindo Pillai 
Acked-by: Tony Cheng 
Signed-off-by: Alex Deucher

drm/amd/display: check if REFCLK_CNTL register is present

2020-04-28T20:42:45+00:00

Check before programming the register since it isn't present on
all IPs using this code.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Bernstein 
Acked-by: Aurabindo Pillai 
Signed-off-by: Alex Deucher

drm/amdgpu: bump version for invalidate L2 before SDMA IBs

2020-04-28T19:58:31+00:00

This fixes GPU hangs due to cache coherency issues.
Bump the driver version. Split out from the original patch.

Signed-off-by: Marek Olšák 
Reviewed-by: Christian König 
Tested-by: Pierre-Eric Pelloux-Prayer 
Signed-off-by: Alex Deucher

drm/amdgpu: invalidate L2 before SDMA IBs (v2)

2020-04-28T19:58:12+00:00

This fixes GPU hangs due to cache coherency issues.

v2: Split the version bump to a separate patch

Signed-off-by: Marek Olšák 
Reviewed-by: Christian König 
Tested-by: Pierre-Eric Pelloux-Prayer 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org

drm/amd/powerplay: avoid using pm_en before it is initialized revised

2020-04-28T19:29:08+00:00

hwmgr->pm_en is initialized at hwmgr_hw_init.

during amdgpu_device_init, there is amdgpu_asic_reset that calls to
soc15_asic_reset (for V320 usecase, Vega10 asic), in which:
1) soc15_asic_reset_method calls to pp_get_asic_baco_capability (pm_en)
2) soc15_asic_baco_reset calls to pp_set_asic_baco_state (pm_en)

pm_en is used in the above two cases while it has not yet been initialized

So avoid using pm_en in the above two functions for V320 passthrough.

Reviewed-by: Evan Quan 
Signed-off-by: Tiecheng Zhou 
Signed-off-by: Alex Deucher

Revert "drm/amd/powerplay: avoid using pm_en before it is initialized"

2020-04-28T19:28:24+00:00

This reverts commit c5207876232649ca5e5ddd6f966d2da75ffded8f.

The commit being reverted changed the wrong place, it should have
changed in func get_asic_baco_capability.

Reviewed-by: Evan Quan 
Signed-off-by: Tiecheng Zhou 
Signed-off-by: Alex Deucher

drm/amd/display: Fix green screen issue after suspend

2020-04-24T13:41:32+00:00

[why]
We have seen a green screen after resume from suspend in a Raven system
connected with two displays (HDMI and DP) on X based system. We noticed
that this issue is related to bad DCC metadata from user space which may
generate hangs and consequently an underflow on HUBP. After taking a
deep look at the code path we realized that after resume we try to
restore the commit with the DCC enabled framebuffer but the framebuffer
is no longer valid.

[how]
This problem was only reported on Raven based system and after suspend,
for this reason, this commit adds a new parameter on
fill_plane_dcc_attributes() to give the option of disabling DCC
programmatically. In summary, for disabling DCC we first verify if is a
Raven system and if it is in suspend; if both conditions are true we
disable DCC temporarily, otherwise, it is enabled.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1099
Co-developed-by: Nicholas Kazlauskas 
Signed-off-by: Nicholas Kazlauskas 
Signed-off-by: Rodrigo Siqueira 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org