linux.git/drivers/gpu/drm/amd, branch v4.2-rc5 Linux kernel source tree drm/amdgpu: add new parameter to seperate map and unmap 2015-07-29T20:06:45+00:00 monk.liu monk.liu@amd.com 2015-07-22T05:29:28+00:00 194a33643b1161fe7a054fa9bf43875ae0f6e1e8 Signed-off-by: monk.liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> 
Signed-off-by: monk.liu <monk.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
drm/amdgpu: hdp_flush is not needed for inside IB 2015-07-29T20:06:17+00:00 monk.liu monk.liu@amd.com 2015-07-17T09:10:09+00:00 e722b71a540362eebdbae060430dc5b06b990c38 hdp flush is not needed for IBs that dispatched from kernel inside because there is no video memory host access Signed-off-by: monk.liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> 
hdp flush is not needed for IBs that dispatched from kernel inside
because there is no video memory host access

Signed-off-by: monk.liu <monk.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
drm/amdgpu: different emit_ib for gfx and compute 2015-07-29T20:05:57+00:00 monk.liu monk.liu@amd.com 2015-07-15T09:21:45+00:00 93323131d66db68802e646204c0562cddc81a651 compute ring didn't use const engine byfar, so ignore CE things in compute routine Signed-off-by: monk.liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> 
compute ring didn't use const engine byfar, so ignore CE things in
compute routine

Signed-off-by: monk.liu <monk.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
drm/amdgpu: information leak in amdgpu_info_ioctl() 2015-07-29T19:50:37+00:00 Dan Carpenter dan.carpenter@oracle.com 2015-07-28T15:51:29+00:00 c193fa91b9182465a4a01665ad4096a6cdb4db2d We recently changed the drm_amdgpu_info_device struct so now there is a 4 byte hole at the end. We need to initialize it so we don't disclose secret information from the stack. Fixes: fa92754e9c47 ('drm/amdgpu: add VCE harvesting instance query') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
We recently changed the drm_amdgpu_info_device struct so now there is
a 4 byte hole at the end.  We need to initialize it so we don't disclose
secret information from the stack.

Fixes: fa92754e9c47 ('drm/amdgpu: add VCE harvesting instance query')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: clean up init sequence for failures 2015-07-29T19:50:36+00:00 Alex Deucher alexander.deucher@amd.com 2015-07-28T15:50:31+00:00 8faf0e08d5a78ae5f1752b1d69f97ed70afa625f If we fail during device init, record what state each block is in so that we can tear down clearly. Fixes various problems on device init failure. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
If we fail during device init, record what state each
block is in so that we can tear down clearly.

Fixes various problems on device init failure.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/cz/dpm: properly report UVD and VCE clock levels 2015-07-23T19:10:32+00:00 Alex Deucher alexander.deucher@amd.com 2015-07-22T16:03:50+00:00 acc6a1a69b79fad70c4794a925dbfffa9fd6b21b VCE, UVD DPM work similarly to SCLK DPM. Report the current clock levels for UVD and VCE via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
VCE, UVD DPM work similarly to SCLK DPM.  Report the current
clock levels for UVD and VCE via debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/cz: implement voltage validation properly 2015-07-23T19:09:27+00:00 Alex Deucher alexander.deucher@amd.com 2015-07-14T20:16:29+00:00 f2d52cd4db08db06200176cfebead9778878d4fc CZ uses a different set of registers compared to previous asics and supports separate NB and GFX planes. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
CZ uses a different set of registers compared to previous asics
and supports separate NB and GFX planes.

Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add VCE harvesting instance query 2015-07-23T15:09:45+00:00 Leo Liu leo.liu@amd.com 2015-07-13T16:46:23+00:00 fa92754e9c47cf3e5607c0865f4cf59d090cda37 Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> 
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
drm/amdgpu: implement VCE 3.0 harvesting support (v4) 2015-07-23T15:09:44+00:00 Alex Deucher alexander.deucher@amd.com 2015-07-10T18:16:24+00:00 6a585777c832f45c05d1aa8a4872b2b292a908c2 For boards with bad VCE blocks, only configure the working block. v2: use the harvest info for pipe setup v3: fix mask check as noted by Leo v4: add dGPU support Reviewed-by: Christian König <christian.koenig@amd.com> (v2) Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
For boards with bad VCE blocks, only configure the working
block.

v2: use the harvest info for pipe setup
v3: fix mask check as noted by Leo
v4: add dGPU support

Reviewed-by: Christian König <christian.koenig@amd.com> (v2)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/dce10: Re-set VBLANK interrupt state when enabling a CRTC 2015-07-23T15:09:43+00:00 Michel Dänzer michel.daenzer@amd.com 2015-07-17T02:20:18+00:00 5e6775abb5ce7ada76fa17c67857576176d0b60f This doesn't seem strictly necessary with Tonga right now, but that might change with future power management enhancements. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> 
This doesn't seem strictly necessary with Tonga right now, but that might
change with future power management enhancements.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>