linux.git/drivers/gpu/drm/amd, branch v4.2-rc4 Linux kernel source tree drm/amdgpu/cz/dpm: properly report UVD and VCE clock levels 2015-07-23T19:10:32+00:00 Alex Deucher alexander.deucher@amd.com 2015-07-22T16:03:50+00:00 acc6a1a69b79fad70c4794a925dbfffa9fd6b21b VCE, UVD DPM work similarly to SCLK DPM. Report the current clock levels for UVD and VCE via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
VCE, UVD DPM work similarly to SCLK DPM.  Report the current
clock levels for UVD and VCE via debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/cz: implement voltage validation properly 2015-07-23T19:09:27+00:00 Alex Deucher alexander.deucher@amd.com 2015-07-14T20:16:29+00:00 f2d52cd4db08db06200176cfebead9778878d4fc CZ uses a different set of registers compared to previous asics and supports separate NB and GFX planes. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
CZ uses a different set of registers compared to previous asics
and supports separate NB and GFX planes.

Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add VCE harvesting instance query 2015-07-23T15:09:45+00:00 Leo Liu leo.liu@amd.com 2015-07-13T16:46:23+00:00 fa92754e9c47cf3e5607c0865f4cf59d090cda37 Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> 
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
drm/amdgpu: implement VCE 3.0 harvesting support (v4) 2015-07-23T15:09:44+00:00 Alex Deucher alexander.deucher@amd.com 2015-07-10T18:16:24+00:00 6a585777c832f45c05d1aa8a4872b2b292a908c2 For boards with bad VCE blocks, only configure the working block. v2: use the harvest info for pipe setup v3: fix mask check as noted by Leo v4: add dGPU support Reviewed-by: Christian König <christian.koenig@amd.com> (v2) Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
For boards with bad VCE blocks, only configure the working
block.

v2: use the harvest info for pipe setup
v3: fix mask check as noted by Leo
v4: add dGPU support

Reviewed-by: Christian König <christian.koenig@amd.com> (v2)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/dce10: Re-set VBLANK interrupt state when enabling a CRTC 2015-07-23T15:09:43+00:00 Michel Dänzer michel.daenzer@amd.com 2015-07-17T02:20:18+00:00 5e6775abb5ce7ada76fa17c67857576176d0b60f This doesn't seem strictly necessary with Tonga right now, but that might change with future power management enhancements. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> 
This doesn't seem strictly necessary with Tonga right now, but that might
change with future power management enhancements.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
drm/amdgpu/dce11: Re-set VBLANK interrupt state when enabling a CRTC 2015-07-23T15:09:43+00:00 Michel Dänzer michel.daenzer@amd.com 2015-07-16T01:45:10+00:00 d84b272a12a6aa96897372449e47e57f72f2730f Something (ATOM BIOS?) seems to be clobbering the LB_INTERRUPT_MASK register while the CRTC is off, which caused e.g. glxgears or gnome-shell to hang after a modeset. Reviewed-and-Tested-by: Alex Deucher <alexander.deucher@amd.com> Tested-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> 
Something (ATOM BIOS?) seems to be clobbering the LB_INTERRUPT_MASK
register while the CRTC is off, which caused e.g. glxgears or
gnome-shell to hang after a modeset.

Reviewed-and-Tested-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
drm/amdgpu/dce8: Re-set VBLANK interrupt state when enabling a CRTC 2015-07-16T16:39:44+00:00 Michel Dänzer michel.daenzer@amd.com 2015-07-09T09:24:24+00:00 1002d71841d52b2390c82c2bc18922ac21fbd090 Something (ATOM BIOS?) seems to be clobbering the LB_INTERRUPT_MASK register while the CRTC is off, which caused e.g. glxgears or gnome-shell to hang after a modeset. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> 
Something (ATOM BIOS?) seems to be clobbering the LB_INTERRUPT_MASK
register while the CRTC is off, which caused e.g. glxgears or
gnome-shell to hang after a modeset.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
drm/amdgpu/cz: silence some dpm debug output 2015-07-16T16:39:43+00:00 Alex Deucher alexander.deucher@amd.com 2015-07-14T21:37:48+00:00 1a45e8a11b3df30800618e57ecb0fb41b3a98ff1 Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/cz: store the forced dpm level 2015-07-16T16:39:42+00:00 Alex Deucher alexander.deucher@amd.com 2015-07-14T16:29:00+00:00 58829aa67da95d03bcca7605d2556361a1785a08 So the selected forced level shows up properly in sysfs. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
So the selected forced level shows up properly in sysfs.

Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/cz: unforce dpm levels before forcing to low/high 2015-07-16T16:39:41+00:00 Alex Deucher alexander.deucher@amd.com 2015-07-14T16:26:41+00:00 85cfe096552b7792032105dbcedeab019ac4c26e This is necessary to properly reset the min/max limits before clamping them otherwise we may get improper clamping depending on what what was the last forced level. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This is necessary to properly reset the min/max limits before
clamping them otherwise we may get improper clamping depending
on what what was the last forced level.

Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>