linux.git/drivers/gpu/drm/amd/powerplay, branch v5.6 Linux kernel source tree drm/amdgpu/powerplay: nv1x, renior copy dcn clock settings of watermark to smu during boot up 2020-03-10T21:31:10+00:00 Hersen Wu hersenxs.wu@amd.com 2020-02-13T15:42:25+00:00 1d2686d417c5998af3817f93be01745b3db57ecd dc to pplib interface is changed for navi1x, renoir. display_config_changed is not called by dc anymore. smu_write_watermarks_table is not executed for navi1x, renoir during boot up. solution: call smu_write_watermarks_table just after dc pass watermark clock settings to pplib Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
dc to pplib interface is changed for navi1x, renoir.
display_config_changed is not called by dc anymore.
smu_write_watermarks_table is not executed for navi1x, renoir
during boot up.

solution: call smu_write_watermarks_table just after dc pass
watermark clock settings to pplib

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/powerplay: map mclk to fclk for COMBINATIONAL_BYPASS case 2020-03-05T14:42:08+00:00 Prike Liang Prike.Liang@amd.com 2020-03-04T02:36:21+00:00 ab65a371dd5f5cba6bd9a58a1a6d4115a71cc5c9 When hit COMBINATIONAL_BYPASS the mclk will be bypass and can export fclk frequency to user usage. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org 
When hit COMBINATIONAL_BYPASS the mclk will be bypass and can export
fclk frequency to user usage.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drm/amd/powerplay: fix pre-check condition for setting clock range 2020-03-05T14:42:08+00:00 Prike Liang Prike.Liang@amd.com 2020-03-02T01:36:15+00:00 80381d40c9bf5218db06a7d7246c5478c95987ee This fix will handle some MP1 FW issue like as mclk dpm table in renoir has a reverse dpm clock layout and a zero frequency dpm level as following case. cat pp_dpm_mclk 0: 1200Mhz 1: 1200Mhz 2: 800Mhz 3: 0Mhz Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org 
This fix will handle some MP1 FW issue like as mclk dpm table in renoir has a reverse
dpm clock layout and a zero frequency dpm level as following case.

cat pp_dpm_mclk
0: 1200Mhz
1: 1200Mhz
2: 800Mhz
3: 0Mhz

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drm/amdgpu: fix memory leak during TDR test(v2) 2020-02-25T16:30:01+00:00 Monk Liu Monk.Liu@amd.com 2020-02-08T11:01:21+00:00 4829f89855f1d3a3d8014e74cceab51b421503db fix system memory leak v2: fix coding style Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
fix system memory leak

v2:
fix coding style

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/powerplay: always refetch the enabled features status on dpm enablement 2020-02-14T17:58:58+00:00 Evan Quan evan.quan@amd.com 2020-02-11T04:39:53+00:00 aad4e2dbe543bc1633bc208ac7bddc4f0bb185ba Otherwise, the cached dpm features status may be inconsistent under some case(e.g. baco reset of Navi asic). Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Otherwise, the cached dpm features status may be inconsistent under some
case(e.g. baco reset of Navi asic).

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu:/navi10: use the ODCAP enum to index the caps array 2020-02-11T20:42:33+00:00 Alex Deucher alexander.deucher@amd.com 2020-02-06T19:53:06+00:00 e33a8cfda5198fc09554fdd77ba246de42c886bd Rather than the FEATURE_ID flags. Avoids a possible reading past the end of the array. Reviewed-by: Evan Quan <evan.quan@amd.com> Reported-by: Aleksandr Mezin <mezin.alexander@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 5.5.x 
Rather than the FEATURE_ID flags.  Avoids a possible reading past
the end of the array.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Reported-by: Aleksandr Mezin <mezin.alexander@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 5.5.x
drm/amdgpu: update smu_v11_0_pptable.h 2020-02-11T20:41:06+00:00 Alex Deucher alexander.deucher@amd.com 2020-02-06T19:46:34+00:00 c1d66bc2e531b4ed3a9464b8e87144cc6b2fd63f Update to the latest changes. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 5.5.x 
Update to the latest changes.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 5.5.x
drm/amdgpu: update default voltage for boot od table for navi1x 2020-02-05T04:30:38+00:00 Alex Deucher alexander.deucher@amd.com 2020-02-04T14:07:19+00:00 7b913a76a6cdda87e538df50df496624407373bf It needed to be updated as well so it will show the proper values if you reset to the defaults. Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
It needed to be updated as well so it will show the proper values
if you reset to the defaults.

Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/smu10: fix smu10_get_clock_by_type_with_voltage 2020-02-04T15:37:52+00:00 Alex Deucher alexander.deucher@amd.com 2020-01-29T17:42:57+00:00 1064ad4aeef94f51ca230ac639a9e996fb7867a0 Cull out 0 clocks to avoid a warning in DC. Bug: https://gitlab.freedesktop.org/drm/amd/issues/963 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Cull out 0 clocks to avoid a warning in DC.

Bug: https://gitlab.freedesktop.org/drm/amd/issues/963
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/smu10: fix smu10_get_clock_by_type_with_latency 2020-02-04T15:37:52+00:00 Alex Deucher alexander.deucher@amd.com 2020-01-28T18:19:51+00:00 4d0a72b66065dd7e274bad6aa450196d42fd8f84 Only send non-0 clocks to DC for validation. This mirrors what the windows driver does. Bug: https://gitlab.freedesktop.org/drm/amd/issues/963 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Only send non-0 clocks to DC for validation.  This mirrors
what the windows driver does.

Bug: https://gitlab.freedesktop.org/drm/amd/issues/963
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>