linux.git/drivers/gpu/drm/amd/pm, branch v5.15-rc2

drm/amd/pm: fix runpm hang when amdgpu loaded prior to sound driver

2021-09-16T13:56:24+00:00

Current RUNPM mechanism relies on PMFW to master the timing for BACO
in/exit. And that needs cooperation from sound driver for dstate
change notification for function 1(audio). Otherwise(on sound driver
missing), BACO cannot be kicked in correctly and hang will be observed
on RUNPM exit.

By switching back to legacy message way on sound driver missing,
we are able to fix the runpm hang observed for the scenario below:
amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded

Signed-off-by: Evan Quan 
Reported-and-tested-by: Pierre-Eric Pelloux-Prayer 
Reviewed-by: Lijo Lazar 
Reviewed-by: Guchun Chen 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org

drm/amdgpu: add manual sclk/vddc setting support for cyan skilfish(v3)

2021-09-16T13:56:23+00:00

Add manual sclk/vddc setting supoort via pp_od_clk_voltage sysfs
to maintain consistency with other asics. As cyan skillfish doesn't
support DPM, there is only a single frequency and voltage to adjust.

v2: maintain consistency and add command guide.
v3: adjust user settings storage and coding style.

Command guide:
echo vc point sclk vddc > pp_od_clk_voltage
	"vc"    - sclk voltage curve
	"point" - must be 0
	"sclk"  - target value of sclk(MHz), should be in safe range
	"vddc"  - target value of vddc(mV), a 6.25(mV) stepping is
		  recommended and should be in safe range (the real
		  vddc is an approximation of target value)
echo c > pp_od_clk_voltage
	"c"	- commit the changes of sclk and vddc, only after
		  the commit command, the target values set by "vc"
		  command will take effect
echo r > pp_od_clk_voltage
	"r" 	- reset sclk and vddc to default value, a subsequent
		  commit command is needed to take effect

Example:
1) Check default sclk and vddc
	$ cat pp_od_clk_voltage
	OD_SCLK:
	0: 1800Mhz *
	OD_VDDC:
	0: 862mV *
	OD_RANGE:
	SCLK:    1000Mhz       2000Mhz
	VDDC:     700mV        1129mV
2) Set sclk to 1500MHz and vddc to 700mV
	$ echo vc 0 1500 700 > pp_od_clk_voltage
	$ echo c > pp_od_clk_voltage
	$ cat pp_od_clk_voltage
	OD_SCLK:
	0: 1500Mhz *
	OD_VDDC:
	0: 693mV *
	OD_RANGE:
	SCLK:    1000Mhz       2000Mhz
	VDDC:     700mV        1129mV
3) Reset sclk and vddc to default
	$ echo r > pp_od_clk_voltage
	$ echo c > pp_od_clk_voltage
	$ cat pp_od_clk_voltage
	OD_SCLK:
	0: 1800Mhz *
	OD_VDDC:
	0: 874mV *
	OD_RANGE:
	SCLK:    1000Mhz       2000Mhz
	VDDC:     700mV        1129mV
NOTE:
We don't specify an explicit safe range, you can set any values
between min and max at your own risk. Enjoy!

Signed-off-by: Lang Yu 
Reviewed-by: Lijo Lazar 
Reviewed-by: Huang Rui 
Signed-off-by: Alex Deucher

drm/amdgpu: add some pptable funcs for cyan skilfish(v3)

2021-09-16T13:56:23+00:00

Add print_clk_levels and read_sensor pptable funcs for
cyan skilfish.

v2: keep consitency and add get_gpu_metrics callback.
v3: use sysfs_emit_at() in sysfs show function.

Signed-off-by: Lang Yu 
Reviewed-by: Huang Rui 
Signed-off-by: Alex Deucher

drm/amdgpu: update SMU driver interface for cyan skilfish(v3)

2021-09-16T13:56:23+00:00

Add SmuMetrics_t definition for cyan skilfish.

v2: update SmuMetrics_t definition.
v3: cleanup and rearrange the order of fields.

Signed-off-by: Lang Yu 
Reviewed-by: Huang Rui 
Signed-off-by: Alex Deucher

drm/amdgpu: update SMU PPSMC for cyan skilfish

2021-09-16T13:56:23+00:00

Add some PPSMC MSGs for cyan skilfish.

Signed-off-by: Lang Yu 
Reviewed-by: Huang Rui 
Signed-off-by: Alex Deucher

drm/amdgpu: fix sysfs_emit/sysfs_emit_at warnings(v2)

2021-09-16T13:56:23+00:00

sysfs_emit and sysfs_emit_at requrie a page boundary
aligned buf address. Make them happy!

v2: use an inline function.

Warning Log:
[  492.545174] invalid sysfs_emit_at: buf:00000000f19bdfde at:0
[  492.546416] WARNING: CPU: 7 PID: 1304 at fs/sysfs/file.c:765 sysfs_emit_at+0x4a/0xa0
[  492.654805] Call Trace:
[  492.655353]  ? smu_cmn_get_metrics_table+0x40/0x50 [amdgpu]
[  492.656780]  vangogh_print_clk_levels+0x369/0x410 [amdgpu]
[  492.658245]  vangogh_common_print_clk_levels+0x77/0x80 [amdgpu]
[  492.659733]  ? preempt_schedule_common+0x18/0x30
[  492.660713]  smu_print_ppclk_levels+0x65/0x90 [amdgpu]
[  492.662107]  amdgpu_get_pp_od_clk_voltage+0x13d/0x190 [amdgpu]
[  492.663620]  dev_attr_show+0x1d/0x40

Signed-off-by: Lang Yu 
Acked-by: Huang Rui 
Signed-off-by: Alex Deucher

drm/amd/pm: fix the issue of uploading powerplay table

2021-09-14T20:15:21+00:00

fix the issue of uploading powerplay table due to the dependancy of rlc.

Signed-off-by: Kenneth Feng 
Reviewed-by: Jack Gui 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org

drm/amdgpu: enable more pm sysfs under SRIOV 1-VF mode

2021-08-31T18:20:41+00:00

Enable pp_num_states, pp_cur_state, pp_force_state, pp_table sysfs under
SRIOV 1-VF scenario.

Signed-off-by: Jiawei Gu 
Signed-off-by: Alex Deucher

drm/amdgpu/swsmu: fix spelling mistake "minimun" -> "minimum"

2021-08-30T19:09:42+00:00

There are three identical spelling mistakes in dev_err messages.
Fix these.

Signed-off-by: Colin Ian King 
Signed-off-by: Alex Deucher

drm/amdgpu: Disable PCIE_DPM on Intel RKL Platform

2021-08-30T19:09:27+00:00

Due to high latency in PCIE clock switching on RKL platforms,
switching the PCIE clock dynamically at runtime can lead to HDMI/DP
audio problems. On newer asics this is handled in the SMU firmware.
For SMU7-based asics, disable PCIE clock switching to avoid the issue.

AMD provide a parameter to disable PICE_DPM.

modprobe amdgpu ppfeaturemask=0xfff7bffb

It's better to contorl PCIE_DPM in amd gpu driver,
switch PCI_DPM by determining intel RKL platform for SMU7-based asics.

Fixes: 1a31474cdb48 ("drm/amd/pm: workaround for audio noise issue")
Ref: https://lists.freedesktop.org/archives/amd-gfx/2021-August/067413.html
Signed-off-by: Koba Ko 
Signed-off-by: Alex Deucher