linux.git/drivers/gpu/drm/amd/pm/inc, branch v5.15

drm/amdgpu: add manual sclk/vddc setting support for cyan skilfish(v3)

2021-09-16T13:56:23+00:00

Add manual sclk/vddc setting supoort via pp_od_clk_voltage sysfs
to maintain consistency with other asics. As cyan skillfish doesn't
support DPM, there is only a single frequency and voltage to adjust.

v2: maintain consistency and add command guide.
v3: adjust user settings storage and coding style.

Command guide:
echo vc point sclk vddc > pp_od_clk_voltage
	"vc"    - sclk voltage curve
	"point" - must be 0
	"sclk"  - target value of sclk(MHz), should be in safe range
	"vddc"  - target value of vddc(mV), a 6.25(mV) stepping is
		  recommended and should be in safe range (the real
		  vddc is an approximation of target value)
echo c > pp_od_clk_voltage
	"c"	- commit the changes of sclk and vddc, only after
		  the commit command, the target values set by "vc"
		  command will take effect
echo r > pp_od_clk_voltage
	"r" 	- reset sclk and vddc to default value, a subsequent
		  commit command is needed to take effect

Example:
1) Check default sclk and vddc
	$ cat pp_od_clk_voltage
	OD_SCLK:
	0: 1800Mhz *
	OD_VDDC:
	0: 862mV *
	OD_RANGE:
	SCLK:    1000Mhz       2000Mhz
	VDDC:     700mV        1129mV
2) Set sclk to 1500MHz and vddc to 700mV
	$ echo vc 0 1500 700 > pp_od_clk_voltage
	$ echo c > pp_od_clk_voltage
	$ cat pp_od_clk_voltage
	OD_SCLK:
	0: 1500Mhz *
	OD_VDDC:
	0: 693mV *
	OD_RANGE:
	SCLK:    1000Mhz       2000Mhz
	VDDC:     700mV        1129mV
3) Reset sclk and vddc to default
	$ echo r > pp_od_clk_voltage
	$ echo c > pp_od_clk_voltage
	$ cat pp_od_clk_voltage
	OD_SCLK:
	0: 1800Mhz *
	OD_VDDC:
	0: 874mV *
	OD_RANGE:
	SCLK:    1000Mhz       2000Mhz
	VDDC:     700mV        1129mV
NOTE:
We don't specify an explicit safe range, you can set any values
between min and max at your own risk. Enjoy!

Signed-off-by: Lang Yu 
Reviewed-by: Lijo Lazar 
Reviewed-by: Huang Rui 
Signed-off-by: Alex Deucher

drm/amdgpu: update SMU driver interface for cyan skilfish(v3)

2021-09-16T13:56:23+00:00

Add SmuMetrics_t definition for cyan skilfish.

v2: update SmuMetrics_t definition.
v3: cleanup and rearrange the order of fields.

Signed-off-by: Lang Yu 
Reviewed-by: Huang Rui 
Signed-off-by: Alex Deucher

drm/amdgpu: update SMU PPSMC for cyan skilfish

2021-09-16T13:56:23+00:00

Add some PPSMC MSGs for cyan skilfish.

Signed-off-by: Lang Yu 
Reviewed-by: Huang Rui 
Signed-off-by: Alex Deucher

drm/amd/pm: And destination bounds checking to struct copy

2021-08-30T18:59:34+00:00

In preparation for FORTIFY_SOURCE performing compile-time and run-time
field bounds checking for memcpy(), memmove(), and memset(), avoid
intentionally writing across neighboring fields.

The "Board Parameters" members of the structs:
	struct atom_smc_dpm_info_v4_5
	struct atom_smc_dpm_info_v4_6
	struct atom_smc_dpm_info_v4_7
	struct atom_smc_dpm_info_v4_10
are written to the corresponding members of the corresponding PPTable_t
variables, but they lack destination size bounds checking, which means
the compiler cannot verify at compile time that this is an intended and
safe memcpy().

Since the header files are effectively immutable[1] and a struct_group()
cannot be used, nor a common struct referenced by both sides of the
memcpy() arguments, add a new helper, amdgpu_memcpy_trailing(), to
perform the bounds checking at compile time. Replace the open-coded
memcpy()s with amdgpu_memcpy_trailing() which includes enough context
for the bounds checking.

"objdump -d" shows no object code changes.

[1] https://lore.kernel.org/lkml/e56aad3c-a06f-da07-f491-a894a570d78f@amd.com

Cc: "Christian König" 
Cc: "Pan, Xinhui" 
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: Hawking Zhang 
Cc: Feifei Xu 
Cc: Likun Gao 
Cc: Jiawei Gu 
Cc: Evan Quan 
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Lijo Lazar 
Acked-by: Alex Deucher 
Signed-off-by: Kees Cook 
Signed-off-by: Alex Deucher

drm/amd/pm: drop the unnecessary intermediate percent-based transition

2021-08-16T19:35:56+00:00

Currently, the readout of fan speed pwm is transited into percent-based
and then pwm-based. However, the transition into percent-based is totally
unnecessary and make the final output less accurate.

Signed-off-by: Evan Quan 
Reviewed-by: Lijo Lazar 
Signed-off-by: Alex Deucher

drm/amd/pm: correct the fan speed RPM retrieving

2021-08-16T19:35:56+00:00

The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed
PWM and RPM is not true for SMU11 ASICs. So, we need a new way to
retrieving the fan speed RPM.

Signed-off-by: Evan Quan 
Reviewed-by: Lijo Lazar 
Signed-off-by: Alex Deucher

drm/amd/pm: correct the fan speed PWM retrieving

2021-08-16T19:35:56+00:00

The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed
PWM and RPM is not true for SMU11 ASICs. So, we need a new way to
retrieving the fan speed PWM.

Signed-off-by: Evan Quan 
Reviewed-by: Lijo Lazar 
Signed-off-by: Alex Deucher

drm/amd/pm: record the RPM and PWM based fan speed settings

2021-08-16T19:35:56+00:00

As the relationship "PWM = RPM / smu->fan_max_rpm" between fan speed
PWM and RPM is not true for SMU11 ASICs. So, both the RPM and PWM
settings need to be saved.

Signed-off-by: Evan Quan 
Reviewed-by: Lijo Lazar 
Signed-off-by: Alex Deucher

drm/amd/pm: correct the fan speed RPM setting

2021-08-16T19:35:56+00:00

The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed
PWM and RPM is not true for SMU11 ASICs. So, we need a new way to
perform the fan speed RPM setting.

Signed-off-by: Evan Quan 
Reviewed-by: Lijo Lazar 
Signed-off-by: Alex Deucher

drm/amd/pm: correct DPM_XGMI/VCN_DPM feature name

2021-08-16T19:17:17+00:00

the following feature is wrong, it will cause sysnode of pp_features show error:
1. DPM_XGMI
2. VCN_DPM

Signed-off-by: Kevin Wang 
Reviewed-by: Lijo Lazar 
Signed-off-by: Alex Deucher