linux.git/drivers/gpu/drm/amd/include/asic_reg, branch v7.2-rc2 Linux kernel source tree drm/amd: Add register header files for DCN42B 2026-06-03T17:43:48+00:00 Matthew Stewart Matthew.Stewart2@amd.com 2026-05-18T22:12:26+00:00 1a1751507e39cd6388257ae93af45a8e5a0d3e97 [Why & How] Add register headers for: - clk 15.0.5 - dcn 4.2.1 - dpcs 4.0.1 - nbio 7.15.5 v2: add in missing license (Alex) Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[Why & How]
Add register headers for:

- clk 15.0.5
- dcn 4.2.1
- dpcs 4.0.1
- nbio 7.15.5

v2: add in missing license (Alex)

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/vpe: add new vpe v2.0.0 register offset and sh/mask 2026-05-11T20:15:51+00:00 Caden Chien chih-wei.chien@amd.com 2026-04-22T10:02:25+00:00 dad6fe3f7c4e6af5875e8d0710afff2b4a0f2c6a New offset and sh/mask are added for vpe v2.0.0 Acked-by: Roy Chan <Roy.Chan@amd.com> Signed-off-by: Caden Chien <chih-wei.chien@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
New offset and sh/mask are added for vpe v2.0.0

Acked-by: Roy Chan <Roy.Chan@amd.com>
Signed-off-by: Caden Chien <chih-wei.chien@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add FRL registers for DCN316 2026-05-11T20:15:28+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2023-06-07T21:22:45+00:00 b0054327595767aec4726929e6ddb94b5d31334f Add the required FRL registers for DCN316. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add the required FRL registers for DCN316.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add FRL registers for DCN315 2026-05-11T20:15:25+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2023-06-07T20:38:26+00:00 14c6da24af6a049c733ef315a5308448b9520f2c Add the required FRL registers for DCN315. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add the required FRL registers for DCN315.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add FRL register for DCN303 2026-05-11T20:15:23+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2023-06-07T20:11:10+00:00 26e4c6b0622683e26130ab9ccbc18f28d52187ac Add all the required registers to support FRL on DCN303. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add all the required registers to support FRL on DCN303.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add FRL register for DCN302 2026-05-11T20:15:20+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2023-06-07T19:53:28+00:00 bcd7f8081d8bd69cdfd9bf039a0c5fe31742f589 Add the required FRL registers for DCN302. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add the required FRL registers for DCN302.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add the necessary FRL registers for DCN314 2026-05-11T20:15:16+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2023-06-07T19:33:03+00:00 8a03fad66224a38839322d27436e41aadf8f0874 Add all the required registers to support FRL on DCN314. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add all the required registers to support FRL on DCN314.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Introduce FRL registers for DCN32 2026-05-11T20:15:13+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2023-05-18T20:43:39+00:00 332b9fe92cdd1251a94c560870dad96ee319b368 This commit add the basic set of FRL registers associated with DCN32. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This commit add the basic set of FRL registers associated with DCN32.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add FRL registers for DCN321 2026-05-11T20:15:11+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2023-05-19T00:24:02+00:00 5bad9d8a1e70667be030dceb06257f472407777a Add the required DCN3.2.1 registers to enable FRL in this ASIC. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add the required DCN3.2.1 registers to enable FRL in this ASIC.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add required FRL registers for DCN31 2026-05-11T20:15:07+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2023-05-18T19:49:27+00:00 5dfcaecc7e1f7cd54134b093993aa3449e79afae This commit introduces multiple hardware registers necessary to enable FRL on AMD devices. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This commit introduces multiple hardware registers necessary to enable
FRL on AMD devices.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>