linux.git/drivers/gpu/drm/amd/include/asic_reg, branch v6.10 Linux kernel source tree drm/amd/display: Add some missing HDMI registers for DCN3x 2024-04-26T21:22:42+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2024-04-09T21:25:23+00:00 5e66f6eaa290093c4542ed216c298000713f92e5 This commit add some missing HDMI control registers to DCN3x. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This commit add some missing HDMI control registers to DCN3x.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add missing debug registers for DCN2/3/3.1 2024-04-26T21:22:40+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2024-04-09T20:35:19+00:00 71dfa617ea9f18e4585fe78364217cd32b1fc382 This commit add some missing debug registers for DPCS and RDPC debug. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This commit add some missing debug registers for DPCS and RDPC debug.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add support of gfx10 register dump 2024-04-26T21:22:39+00:00 Sunil Khatri sunil.khatri@amd.com 2024-04-16T10:44:12+00:00 c395dbb68b294d1de9a5ac6c9faaf8ac081123c3 Adding gfx10 gc registers to be used for register dump via devcoredump during a gpu reset. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Adding gfx10 gc registers to be used for register
dump via devcoredump during a gpu reset.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add IH_RING1_CFG headers for IH v6.0 2024-04-19T03:46:31+00:00 Sunil Khatri sunil.khatri@amd.com 2024-04-12T09:17:30+00:00 cba9b630f087005a2c9c201e16b5dbf91d51d3c0 Add offsets, mask and shift macros for IH v6.0 which are needed to configure ring1 client irq redirection. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add offsets, mask and shift macros for IH v6.0
which are needed to configure ring1 client irq
redirection.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add missing registers 2024-04-10T02:06:16+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2024-03-22T19:56:26+00:00 be239684b18e1cdcafcf8c7face4a2f562c745ad Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add some missing debug registers 2024-04-10T02:05:50+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2024-03-21T21:51:44+00:00 e7927b2914d40cff609b43a1cf9077e6737a2e27 Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add smuio v14_0_2 ip headers (v4) 2024-03-20T17:38:16+00:00 Hawking Zhang Hawking.Zhang@amd.com 2023-12-19T11:13:00+00:00 c9d7f802e698c03a06cce4bbfbbbeb7b7be26f8a v1: Add smuio v14_0_2 register offset and shift masks header files. (Hawking) v2: Update smuio v14_0_2 register offset and shift masks header files to RE2. (Likun) v3: Update smuio v14_0_2 register offset and shift masks header files to RE2.5. (Likun) v4: Clean up smuio v14_0_2 ip headers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
v1: Add smuio v14_0_2 register offset and shift masks
    header files. (Hawking)
v2: Update smuio v14_0_2 register offset and shift masks
    header files to RE2. (Likun)
v3: Update smuio v14_0_2 register offset and shift masks
    header files to RE2.5. (Likun)
v4: Clean up smuio v14_0_2 ip headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add missing registers and offset 2024-03-20T17:38:13+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2024-03-11T23:20:01+00:00 0ba7ad7e42ea9d38c39d98137af3ad6a18f2ee8f [Why & How] Registers and offset are missing. Add it back Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[Why & How]
Registers and offset are missing. Add it back

Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add new bit definitions for GC 9.0 PROTECTION_FAULT_STATUS 2024-03-20T17:37:36+00:00 Tao Zhou tao.zhou1@amd.com 2024-02-19T07:29:51+00:00 b7b23877a2479951578dcaa8523314ed2cceccc3 Add UCE and FED bit definitions. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add UCE and FED bit definitions.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add pcie v6_1_0 ip headers (v5) 2024-03-07T20:32:38+00:00 Hawking Zhang Hawking.Zhang@amd.com 2023-07-03T13:54:17+00:00 b9e9b8eaaf87c20cc7e68234a9b0efe417590699 v1: Add pcie v6_1_0 register offset and shift masks header files. (Hawking) v2: Update pcie v6_1_0 register offset and shift masks header files to RE2. (Likun) v3: Update pcie v6_1_0 register offset and shift masks header files to RE2.5. (Likun) v4: Update pcie v6_1_0 register offset and shift masks header files to RE3. (Likun) v5: Updates (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
v1: Add pcie v6_1_0 register offset and shift masks
    header files. (Hawking)
v2: Update pcie v6_1_0 register offset and shift masks
    header files to RE2. (Likun)
v3: Update pcie v6_1_0 register offset and shift masks
    header files to RE2.5. (Likun)
v4: Update pcie v6_1_0 register offset and shift masks
    header files to RE3. (Likun)
v5: Updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>