linux.git/drivers/gpu/drm/amd/display, branch v5.6-rc4

drm/amdgpu/display: clean up hdcp workqueue handling

2020-02-19T16:03:24+00:00

Use the existence of the workqueue itself to determine when to
enable HDCP features rather than sprinkling asic checks all over
the code.  Also add a check for the existence of the hdcp
workqueue in the irq handling on the off chance we get and HPD
RX interrupt with the CP bit set.  This avoids a crash if
the driver doesn't support HDCP for a particular asic.

Fixes: 96a3b32e67236f ("drm/amd/display: only enable HDCP for DCN+")
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206519
Reviewed-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher

drm/amd/display: fix backwards byte order in rx_caps.

2020-02-14T17:58:58+00:00

We were using incorrect byte order after we started using the drm_defines
So fix it.

Fixes: 02837a91ae75 ("drm/amd/display: add and use defines from drm_hdcp.h")
Signed-off-by: JinZe.Xu 
Signed-off-by: Bhawanpreet Lakha 
Reviewed-by: Wenjing Liu 
Signed-off-by: Alex Deucher

drm/amd/display: DCN2.x Do not program DPPCLK if same value

2020-02-11T20:39:45+00:00

[WHY]
Programming DPPCLK to the same value currently set may cause
underflow while playing video in certain conditions.

[HOW]
Only program DPPCLK if clock is not the same as the
previous value programmed.

Signed-off-by: Sung Lee 
Reviewed-by: Yongqiang Sun 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

drm/amd/display: Don't map ATOM_ENABLE to ATOM_INIT

2020-02-11T20:38:27+00:00

[Why]
In DCN hardware sequencer we do actually call ATOM_INIT correctly per
pipe. The workaround is not necessary for command table offloading.

[How]
Drop the workaround since it's not needed.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Chris Park 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher

amdgpu: Prevent build errors regarding soft/hard-float FP ABI tags

2020-02-11T20:35:22+00:00

On PowerPC, the compiler will tag object files with whether they
use hard or soft float FP ABI and whether they use 64 or 128-bit
long double ABI. On systems with 64-bit long double ABI, a tag
will get emitted whenever a double is used, as on those systems
a long double is the same as a double. This will prevent linkage
as other files are being compiled with hard-float.

On ppc64, this code will never actually get used for the time
being, as the only currently existing hardware using it are the
Renoir APUs. Therefore, until this is testable and can be fixed
properly, at least make sure the build will not fail.

Signed-off-by: Daniel Kolesa 
Signed-off-by: Alex Deucher

drm/amd/display: Add initialitions for PLL2 clock source

2020-02-11T20:09:18+00:00

[Why]
Starting from 14nm, the PLL is built into the PHY and the PLL is mapped
to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not
initialized. This causes DP to HDMI dongle to not light up the display.

[How]
Initializations added for PLL2 when creating resources.

Signed-off-by: Isabel Zhang 
Reviewed-by: Eric Yang 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher

drm/amd/display: Limit minimum DPPCLK to 100MHz.

2020-02-11T20:08:13+00:00

[Why]
Underflow is observed when plug in a 4K@60 monitor with
1366x768 eDP due to DPPCLK is too low.

[How]
Limit minimum DPPCLK to 100MHz.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Eric Yang 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher

drm/amd/display: Check engine is not NULL before acquiring

2020-02-11T20:07:03+00:00

[Why]
Engine can be NULL in some cases, so we must not acquire it.

[How]
Check for NULL engine before acquiring.

Signed-off-by: Aric Cyr 
Reviewed-by: Harry Wentland 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher

drm/amd/display: Use dcfclk to populate watermark ranges

2020-02-11T17:15:02+00:00

[WHY & HOW]
Previously drain clk was unconstrained and fill clk was constrained on fclk.
We want to change it to fill clk unconstrained and drain clock constrained
to dcfclk.

Signed-off-by: Sung Lee 
Reviewed-by: Tony Cheng 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher

drm/amd/display: Do not set optimized_require to false after plane disable

2020-02-11T17:12:31+00:00

[WHY]
The optimized_require flag is needed to set watermarks and clocks lower
in certain conditions. This flag is set to true and then set to false
while programming front end in dcn20.

[HOW]
Do not set the flag to false while disabling plane.

Signed-off-by: Sung Lee 
Reviewed-by: Tony Cheng 
Acked-by: Bhawanpreet Lakha 
Signed-off-by: Alex Deucher