linux.git/drivers/gpu/drm/amd/display/dc, branch v6.6-rc2

drm/amd/display: Fix 2nd DPIA encoder Assignment

2023-09-11T22:30:15+00:00

[HOW & Why]
There seems to be an issue with 2nd DPIA acquiring link encoder for tiled displays.
Solution is to remove check for eng_id before we get first dynamic encoder for it

Reviewed-by: Cruise Hung 
Reviewed-by: Meenakshikumar Somasundaram 
Cc: Mario Limonciello 
Cc: Alex Deucher 
Cc: stable@vger.kernel.org
Acked-by: Stylon Wang 
Signed-off-by: Mustapha Ghaddar 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Add DPIA Link Encoder Assignment Fix

2023-09-11T22:30:03+00:00

For DPIA we should have preferred DIG assignment based on DPIA selected
as per the ASIC design.

Reviewed-by: George Shen 
Acked-by: Hamza Mahfooz 
Signed-off-by: Mustapha Ghaddar 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org

drm/amd/display: Don't check registers, if using AUX BL control

2023-09-11T22:19:31+00:00

[Why]
Currently the driver looks DCN registers to access if BL is on or not.
This check is not valid if we are using AUX based brightness control.
This causes driver to not send out "backlight off" command during power off
sequence as it already thinks it is off.

[How]
Only check DCN registers if we aren't using AUX based brightness control.

Reviewed-by: Wenjing Liu 
Acked-by: Stylon Wang 
Signed-off-by: Swapnil Patel 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: limit the v_startup workaround to ASICs older than DCN3.1

2023-09-07T02:08:26+00:00

Since, calling dcn20_adjust_freesync_v_startup() on DCN3.1+ ASICs
can cause the display to flicker and underflow to occur, we shouldn't
call it for them. So, ensure that the DCN version is less than
DCN_VERSION_3_1 before calling dcn20_adjust_freesync_v_startup().

Cc: stable@vger.kernel.org
Reviewed-by: Fangzhi Zuo 
Signed-off-by: Hamza Mahfooz 
Signed-off-by: Alex Deucher

Revert "drm/amd/display: Remove v_startup workaround for dcn3+"

2023-09-07T02:08:10+00:00

This reverts commit 3a31e8b89b7240d9a17ace8a1ed050bdcb560f9e.

We still need to call dcn20_adjust_freesync_v_startup() for older DCN3+
ASICs. Otherwise, it can cause DP to HDMI 2.1 PCONs to fail to light up.

Cc: stable@vger.kernel.org
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2809
Reviewed-by: Fangzhi Zuo 
Reviewed-by: Harry Wentland 
Signed-off-by: Hamza Mahfooz 
Signed-off-by: Alex Deucher

drm/amd/display: always switch off ODM before committing more streams

2023-08-31T22:09:14+00:00

ODM power optimization is only supported with single stream. When ODM
power optimization is enabled, we might not have enough free pipes for
enabling other stream. So when we are committing more than 1 stream we
should first switch off ODM power optimization to make room for new
stream and then allocating pipe resource for the new stream.

Cc: stable@vger.kernel.org
Fixes: 59de751e3845 ("drm/amd/display: add ODM case when looking for first split pipe")
Reviewed-by: Dillon Varone 
Acked-by: Hamza Mahfooz 
Signed-off-by: Wenjing Liu 
Signed-off-by: Alex Deucher

drm/amd/display: Remove wait while locked

2023-08-31T22:08:19+00:00

[Why]
We wait for mpc idle while in a locked state, leading to potential
deadlock.

[What]
Move the wait_for_idle call to outside of HW lock. This and a
call to wait_drr_doublebuffer_pending_clear are moved added to a new
static helper function called wait_for_outstanding_hw_updates, to make
the interface clearer.

Cc: stable@vger.kernel.org
Fixes: 8f0d304d21b3 ("drm/amd/display: Do not commit pipe when updating DRR")
Reviewed-by: Jun Lei 
Acked-by: Hamza Mahfooz 
Signed-off-by: Gabe Teeger 
Signed-off-by: Alex Deucher

drm/amd/display: update blank state on ODM changes

2023-08-31T22:06:41+00:00

When we are dynamically adding new ODM slices, we didn't update
blank state, if the pipe used by new ODM slice is previously blanked,
we will continue outputting blank pixel data on that slice causing
right half of the screen showing blank image.

The previous fix was a temporary hack to directly update current state
when committing new state. This could potentially cause hw and sw
state synchronization issues and it is not permitted by dc commit
design.

Cc: stable@vger.kernel.org
Fixes: 7fbf451e7639 ("drm/amd/display: Reinit DPG when exiting dynamic ODM")
Reviewed-by: Dillon Varone 
Acked-by: Hamza Mahfooz 
Signed-off-by: Wenjing Liu 
Signed-off-by: Alex Deucher

drm/amd/display: Add smu write msg id fail retry process

2023-08-31T22:06:25+00:00

A benchmark stress test (12-40 machines x 48hours) found that DCN315 has
cases where DC writes to an indirect register to set the smu clock msg
id, but when we go to read the same indirect register the returned msg
id doesn't match with what we just set it to. So, to fix this retry the
write until the register's value matches with the requested value.

Cc: stable@vger.kernel.org # 6.1+
Fixes: f94903996140 ("drm/amd/display: Add DCN315 CLK_MGR")
Reviewed-by: Charlene Liu 
Acked-by: Hamza Mahfooz 
Signed-off-by: Fudong Wang 
Signed-off-by: Alex Deucher

Partially revert "drm/amd/display: update add plane to context logic with a new algorithm"

2023-08-31T22:05:26+00:00

This partially reverts commit 460ea8980511 ("drm/amd/display: update add
plane to context logic with a new algorithm").

The new secondary pipe allocation logic triggers an issue with a
specific hardware state transition and causes a frame of corruption when
toggling between windowed MPO and ODM desktop only mode. Ideally hwss is
supposed to handle this scenario. We are temporarily reverting the logic
and investigate the root cause why this transition would cause
corruptions.

Fixes: 460ea8980511 ("drm/amd/display: update add plane to context logic with a new algorithm")
Reviewed-by: Martin Leung 
Acked-by: Hamza Mahfooz 
Signed-off-by: Wenjing Liu 
Signed-off-by: Alex Deucher