linux.git/drivers/gpu/drm/amd/display/dc, branch v6.1

drm/amd/display: fix array index out of bound error in DCN32 DML

2022-12-07T17:21:53+00:00

[Why&How]
LinkCapacitySupport array is indexed with the number of voltage states and
not the number of max DPPs. Fix the error by changing the array
declaration to use the correct (larger) array size of total number of
voltage states.

Signed-off-by: Aurabindo Pillai 
Reviewed-by: Rodrigo Siqueira 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org # 6.0.x

drm/amd/display: Fix rotated cursor offset calculation

2022-11-23T14:01:53+00:00

[Why]
Underflow is observed when cursor is still enabled when the cursor
rectangle is outside the bounds of it's surface viewport.

[How]
Update parameters used to determine when cursor should be disabled.

Reviewed-by: Martin Leung 
Acked-by: Brian Chang 
Signed-off-by: David Galiffi 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Use new num clk levels struct for max mclk index

2022-11-23T14:01:53+00:00

[WHY?]
When calculating watermark and dlg values, the max mclk level index and
associated speed are needed to find the correlated dummy latency value.
Currently the incorrect index is given due to a clock manager refactor.

[HOW?]
Use num_memclk_level from num_entries_per_clk struct for getting the correct max
mem speed.

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Dillon Varone 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Avoid setting pixel rate divider to N/A

2022-11-23T14:01:53+00:00

[Why]
Pixel rate divider values should never be set to N/A (0xF) as the K1/K2
field is only 1/2 bits wide.

[How]
Set valid divider values for virtual and FRL/DP2 cases.

Reviewed-by: Nicholas Kazlauskas 
Acked-by: Brian Chang 
Signed-off-by: Taimur Hassan 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Use viewport height for subvp mall allocation size

2022-11-23T14:01:53+00:00

[WHY?]
MALL allocation size depends on the viewport height, not the addressable
vertical lines, which will not match when scaling.

[HOW?]
Base MALL allocation size calculations off viewport height.

Reviewed-by: Alvin Lee 
Reviewed-by: Martin Leung 
Acked-by: Brian Chang 
Signed-off-by: Dillon Varone 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Update soc bounding box for dcn32/dcn321

2022-11-23T14:01:53+00:00

[Description]
New values for soc bounding box and dummy pstate.

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Dillon Varone 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org # 6.0.x

drm/amd/dc/dce120: Fix audio register mapping, stop triggering KASAN

2022-11-23T14:01:53+00:00

There's been a very long running bug that seems to have been neglected for
a while, where amdgpu consistently triggers a KASAN error at start:

  BUG: KASAN: global-out-of-bounds in read_indirect_azalia_reg+0x1d4/0x2a0 [amdgpu]
  Read of size 4 at addr ffffffffc2274b28 by task modprobe/1889

After digging through amd's rather creative method for accessing registers,
I eventually discovered the problem likely has to do with the fact that on
my dce120 GPU there are supposedly 7 sets of audio registers. But we only
define a register mapping for 6 sets.

So, fix this and fix the KASAN warning finally.

Signed-off-by: Lyude Paul 
Cc: stable@vger.kernel.org
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher

drm/amd/display: Align dcn314_smu logging with other DCNs

2022-11-21T21:38:14+00:00

[Why]
Assert on non-OK response from SMU is unnecessary.
It was replaced with respective log message on other asics
in the past with commit:
"drm/amd/display: Removing assert statements for Linux"

[How]
Remove assert and add dbg logging as on other DCNs.

Signed-off-by: Roman Li 
Reviewed-by: Saaem Rizvi 
Signed-off-by: Alex Deucher

drm/amd/display: Set max for prefetch lines on dcn32

2022-11-15T18:22:50+00:00

[WHY?]
Max number of lines that can be used for prefetch due to type constraints is
63.75.

[HOW?]
Enforce maximum prefetch lines as 63.75.

Reviewed-by: Jun Lei 
Acked-by: Tom Chung 
Signed-off-by: Dillon Varone 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: use uclk pstate latency for fw assisted mclk validation dcn32

2022-11-15T18:22:20+00:00

[WHY?]
DCN32 uses fclk pstate watermarks for dummy pstate, and must always be
supported.

[HOW?]
Validation needs to be run with fclk pstate latency set
as the dummy pstate latency to get correct prefetch and bandwidth outputs.

Reviewed-by: Jun Lei 
Acked-by: Tom Chung 
Signed-off-by: Dillon Varone 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher