linux.git/drivers/gpu/drm/amd/display/dc, branch v6.0-rc2

drm/amd/display: Include scaling factor for SubVP command

2022-08-16T22:14:20+00:00

[Description]
For SubVP scaling cases, we must include the scaling
info as part of the cmd. This is required when converting
OTG line to HUBP line for the MALL_START_LINE programming.

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Alvin Lee 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: avoid doing vm_init multiple time

2022-08-16T22:09:16+00:00

[why]
this is to ensure that driver will not reprogram hvm_prefetch_req again if
it is done.

Reviewed-by: Martin Leung 
Acked-by: Brian Chang 
Signed-off-by: Charlene Liu 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Use pitch when calculating size to cache in MALL

2022-08-16T22:09:09+00:00

[Description]
Use pitch when calculating size to cache in MALL

Reviewed-by: Samson Tam 
Acked-by: Brian Chang 
Signed-off-by: Alvin Lee 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Don't set DSC for phantom pipes

2022-08-16T22:09:01+00:00

[Description]
Don't set DSC bit for phantom pipes, not
required since phantom pipe don't have
any actual output

Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Alvin Lee 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Update clock table policy for DCN314

2022-08-16T22:08:54+00:00

[Why & How]
Depending on how the clock table is constructed from PMFW we can run
into issues where we don't think we have enough bandwidth available
due to FCLK too low - eg. when the FCLK table contains invalid entries
or a single entry.

We should always pick up the maximum clocks for each state as a final
state in this case to prevent validation from failing if the table is
malformed.

We should also contain sensible defaults in the case where values
are invalid.

Redfine the clock table structures by adding a 314 prefix to make
debugging these issues easier by avoiding symbol name clashes.

Overall this policy more closely aligns to how we did things for 315,
but because of how the voltage rail is setup we should favor keeping
DCFCLK low rather than DISPCLK or DPPCLK - so use the max for those
in every entry.

Reviewed-by: Daniel Miess 
Acked-by: Brian Chang 
Signed-off-by: Nicholas Kazlauskas 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Modify header inclusion pattern

2022-08-16T22:08:42+00:00

[Why]
Recent backport from opensource broke the Nightly tool build
that tests DC and DML for bugs and regressions. This was
because the backport had a header inclusion that was not
consistent with the AMD style of including headers was allowed
to be merged back in DML code that caused tool compilation
failures.

[How]
Modify the way in which the header file in included so that it
is consistent with AMD style of including headers. This then
automatically fixes the tool compilation process and also
helps maintain the code quality and consistency.

Reviewed-by: Alvin Lee 
Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Chaitanya Dhere 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Fix plug/unplug external monitor will hang while playback MPO video

2022-08-16T22:08:36+00:00

[Why]
Pipes for MPO primary and overlay will be power down and power up during
plug/unplug external monitor while MPO video playback.
But the pipes were the same after plug/unplug and should not need to be
power down and power up or it will make page flip interrupt disabled and
cause hang issue.

[How]
Add pipe split change condition that not only check the top pipe pointer
but also check the index of top pipe if both top pipes are available.

Reviewed-by: Sun peng Li 
Acked-by: Brian Chang 
Signed-off-by: Tom Chung 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Add debug parameter to retain default clock table

2022-08-16T22:08:08+00:00

[Why]
Need a way to retain default clock table to aid
the investigation into why 8k@30 display not
lighting up on dcn314

[How]
Use flag to prevent execution of bw_params helper
function and function for updating bw_bounding_box

Reviewed-by: Nicholas Kazlauskas 
Reviewed-by: Jun Lei 
Acked-by: Brian Chang 
Signed-off-by: Daniel Miess 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: do not compare integers of different widths

2022-08-16T22:07:54+00:00

[Why & How]
Increase width of some variables to avoid comparing integers of
different widths.

Reviewed-by: Alvin Lee 
Acked-by: Brian Chang 
Signed-off-by: Josip Pavic 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher

drm/amd/display: Fix pixel clock programming

2022-08-16T22:07:21+00:00

[Why]
Some pixel clock values could cause HDMI TMDS SSCPs to be misaligned
between different HDMI lanes when using YCbCr420 10-bit pixel format.

BIOS functions for transmitter/encoder control take pixel clock in kHz
increments, whereas the function for setting the pixel clock is in 100Hz
increments. Setting pixel clock to a value that is not on a kHz boundary
will cause the issue.

[How]
Round pixel clock down to nearest kHz in 10/12-bpc cases.

Reviewed-by: Aric Cyr 
Acked-by: Brian Chang 
Signed-off-by: Ilya Bakoulin 
Tested-by: Daniel Wheeler 
Signed-off-by: Alex Deucher