linux.git/drivers/gpu/drm/amd/display/dc, branch v5.0-rc2

drm/amd/display: Fix MST dp_blank REG_WAIT timeout

2018-12-20T17:13:35+00:00

Need to blank stream before deallocate MST payload.

[drm:generic_reg_wait [amdgpu]] *ERROR* REG_WAIT timeout 10us * 3000 tries - dce110_stream_encoder_dp_blank line:944
------------[ cut here ]------------
WARNING: CPU: 0 PID: 2201 at /var/lib/dkms/amdgpu/18.50-690240/build/amd/amdgpu/../display/dc/dc_helper.c:249 generic_reg_wait+0xe7/0x160 [amdgpu]
Call Trace:
 dce110_stream_encoder_dp_blank+0x11c/0x180 [amdgpu]
 core_link_disable_stream+0x40/0x230 [amdgpu]
 ? generic_reg_update_ex+0xdb/0x130 [amdgpu]
 dce110_reset_hw_ctx_wrap+0xb7/0x1f0 [amdgpu]
 dce110_apply_ctx_to_hw+0x30/0x430 [amdgpu]
 ? dce110_apply_ctx_for_surface+0x206/0x260 [amdgpu]
 dc_commit_state+0x2ba/0x4d0 [amdgpu]
 amdgpu_dm_atomic_commit_tail+0x297/0xd70 [amdgpu]
 ? amdgpu_bo_pin_restricted+0x58/0x260 [amdgpu]
 ? wait_for_completion_timeout+0x1f/0x120
 ? wait_for_completion_interruptible+0x1c/0x160
 commit_tail+0x3d/0x60 [drm_kms_helper]
 drm_atomic_helper_commit+0xf6/0x100 [drm_kms_helper]
 drm_atomic_connector_commit_dpms+0xe5/0xf0 [drm]
 drm_mode_obj_set_property_ioctl+0x14f/0x250 [drm]
 drm_mode_connector_property_set_ioctl+0x2e/0x40 [drm]
 drm_ioctl+0x1e0/0x430 [drm]
 ? drm_mode_connector_set_obj_prop+0x70/0x70 [drm]
 ? ep_read_events_proc+0xb0/0xb0
 ? ep_scan_ready_list.constprop.18+0x1e6/0x1f0
 ? timerqueue_add+0x52/0x80
 amdgpu_drm_ioctl+0x49/0x80 [amdgpu]
 do_vfs_ioctl+0x90/0x5f0
 SyS_ioctl+0x74/0x80
 do_syscall_64+0x74/0x140
 entry_SYSCALL_64_after_hwframe+0x3d/0xa2
---[ end trace 3ed7b77a97d60f72 ]---

Signed-off-by: Jerry (Fangzhi) Zuo 
Reviewed-by: Hersen Wu 
Acked-by: Harry Wentland 
Acked-by: Alex Deucher 
Tested-by: Lyude Paul 
Signed-off-by: Alex Deucher 
Cc: stable@vger.kernel.org

drm/amd/display: validate extended dongle caps

2018-12-20T17:13:18+00:00

[why]
Some dongle doesn't have a valid extended dongle caps,
but we still set the extended dongle caps to be valid.
This causes validation fails for all timing.

[how]
If no dp_hdmi_max_pixel_clk is provided,
don't use extended dongle caps.

Signed-off-by: Wenjing Liu 
Reviewed-by: Aric Cyr 
Reviewed-by: Jun Lei 
Acked-by: Abdoulaye Berthe 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher

drm/amd/display: Optimize passive update planes.

2018-12-18T23:25:13+00:00

[Why]
passive update planes still spends a litte more
time on some cases.

[How]
Remove unnecessary trace which involving in some register read.
Disable debug output for release build.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher

drm/amd/display: verify lane status before exiting verify link cap

2018-12-18T23:25:13+00:00

[why]
DP LL CTS1.4 4.3.2.1 test failure.

[how]
The failure is caused by not handling DP link loss
hpd short pusle during set mode. The change is to read link status
before set mode link training. If link is lost, re-verify link caps.
Signed-off-by: Wenjing Liu 
Reviewed-by: Jun Lei 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher

drm/amd/display: Fix bug with not updating VSP infoframe

2018-12-18T23:25:13+00:00

[WHY]
Currently, when the VSP infopacket is rebuilt in DM, it is not updated
when being programmed in encoder.

[HOW]
Add new VSP case for update_info_frame

Signed-off-by: SivapiriyanKumarasamy 
Reviewed-by: Anthony Koo 
Acked-by: Krunoslav Kovac 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher

drm/amd/display: Add retry to read ddc_clock pin

2018-12-18T23:25:12+00:00

[WHY]
On customer board, there is one pluse (1v , < 1ms) on
DDC_CLK pin when plug / unplug DP cable. Driver will read
it and config DP to HDMI/DVI dongle.

[HOW]
If there is a real dongle, DDC_CLK should be always pull high.
Try to read again to recovery this special case. Retry times = 3.
Need additional 3ms to detect DP passive dongle(3 failures)

Signed-off-by: Paul Hsieh 
Reviewed-by: Eric Yang 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher

drm/amd/display: Don't skip link training for empty dongle

2018-12-18T23:25:12+00:00

[Why]
Skipping initial link training will result in no verified link cap for
mode enumeration. Some versions of the BIOS seem to have PHY programming
sequence issue as well if initial link training is skipped, resulting in
a softlock in BIOS command table.

[How]
Identify the empty dongle hotplug case, and still do initial link
training.

Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher

drm/amd/display: Wait edp HPD to high in detect_sink

2018-12-18T23:25:12+00:00

[Why]
In 99% user case, edp will be post by vbios.
In 1% / current case: Lenovo don't light up edp panel in vbios
post stage, vbios won't be lit up. Thus in dal when we init DCN
10 hw, we power up edp, then we start detect_sink, but internal
time is too short, when we detect it, HPD is still low, so we don't
detect the edp, and edp shows black.

[How]
When we init hw, we wait edp HPD to high after power up edp.

Signed-off-by: Dale Zhao 
Reviewed-by: Eric Yang 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher

drm/amd/display: fix surface update sequence

2018-12-18T23:25:11+00:00

An earlier change added update of interdependent dlg/ttu params for pipes
not being updated in the current call. The code fails to check if the other
pipes are actually active yet causing an assert.

This change adds a check for surface presence on the pipes before updating
the interdepenednt params.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Nikola Cornij 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher

drm/amd/display: fix YCbCr420 blank color

2018-12-18T23:25:11+00:00

[Why]
YCbCr420 packing format uses two chanels for luma, and 1
channel for both chroma component. Our previous implementation
did not account for this and results in every other pixel having
very high luma value, showing greyish color instead of black.

YCbCr444 = ;  .....
YCbCr420 = ;  .....

[How]
Program the second channel with the black color value for luma
as well.

Signed-off-by: Eric Yang 
Reviewed-by: Hugo Hu 
Acked-by: Leo Li 
Signed-off-by: Alex Deucher