<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/gpu/drm/amd/display/dc/resource, branch for-next</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>drm/amd/display: Add hblank borrowing support</title>
<updated>2024-12-02T23:35:32+00:00</updated>
<author>
<name>Chris Park</name>
<email>chris.park@amd.com</email>
</author>
<published>2024-11-15T20:44:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=0c0a19430bfdfedab437e77b9262e8e62ced384e'/>
<id>0c0a19430bfdfedab437e77b9262e8e62ced384e</id>
<content type='text'>
[WHY]
Some DSC timing failed at bandwidth validation due to hactive
can't be evenly divided on each ODM segment.

[HOW]
Borrow from hblank to increase hactive to support these timing.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Chris Park &lt;chris.park@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[WHY]
Some DSC timing failed at bandwidth validation due to hactive
can't be evenly divided on each ODM segment.

[HOW]
Borrow from hblank to increase hactive to support these timing.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Chris Park &lt;chris.park@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Limit VTotal range to max hw cap minus fp</title>
<updated>2024-12-02T23:35:28+00:00</updated>
<author>
<name>Dillon Varone</name>
<email>dillon.varone@amd.com</email>
</author>
<published>2024-11-13T21:44:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=a29997b7ac1f5c816b543e0c56aa2b5b56baac24'/>
<id>a29997b7ac1f5c816b543e0c56aa2b5b56baac24</id>
<content type='text'>
[WHY &amp; HOW]
Hardware does not support the VTotal to be between fp2 lines of the
maximum possible VTotal, so add a capability flag to track it and apply
where necessary.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Jun Lei &lt;jun.lei@amd.com&gt;
Reviewed-by: Anthony Koo &lt;anthony.koo@amd.com&gt;
Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[WHY &amp; HOW]
Hardware does not support the VTotal to be between fp2 lines of the
maximum possible VTotal, so add a capability flag to track it and apply
where necessary.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Jun Lei &lt;jun.lei@amd.com&gt;
Reviewed-by: Anthony Koo &lt;anthony.koo@amd.com&gt;
Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Add option to retrieve detile buffer size</title>
<updated>2024-12-02T23:35:20+00:00</updated>
<author>
<name>Sung Lee</name>
<email>Sung.Lee@amd.com</email>
</author>
<published>2024-11-14T19:18:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=6a7fd76b949efe40fb6d6677f480e624e0cb6e40'/>
<id>6a7fd76b949efe40fb6d6677f480e624e0cb6e40</id>
<content type='text'>
[WHY]
For better power profiling knowing the detile
buffer size at a given point in time
would be useful.

[HOW]
Add interface to retrieve detile buffer from
dc state.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Signed-off-by: Sung Lee &lt;Sung.Lee@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[WHY]
For better power profiling knowing the detile
buffer size at a given point in time
would be useful.

[HOW]
Add interface to retrieve detile buffer from
dc state.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Signed-off-by: Sung Lee &lt;Sung.Lee@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Add a left edge pixel if in YCbCr422 or YCbCr420 and odm</title>
<updated>2024-12-02T23:35:16+00:00</updated>
<author>
<name>Peterson Guo</name>
<email>peterson.guo@amd.com</email>
</author>
<published>2024-11-08T00:20:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=63e7ee677c74e981257cedfdd8543510d09096ba'/>
<id>63e7ee677c74e981257cedfdd8543510d09096ba</id>
<content type='text'>
[WHY]
On some cards when odm is used, the monitor will have 2 separate pipes
split vertically. When compression is used on the YCbCr colour space on
the second pipe to have correct colours, we need to read a pixel from the
end of first pipe to accurately display colours. Hardware was programmed
properly to account for this extra pixel but it was not calculated
properly in software causing a split screen on some monitors.

[HOW]
The fix adjusts the second pipe's viewport and timings if the pixel
encoding is YCbCr422 or YCbCr420.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: George Shen &lt;george.shen@amd.com&gt;
Signed-off-by: Peterson Guo &lt;peterson.guo@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[WHY]
On some cards when odm is used, the monitor will have 2 separate pipes
split vertically. When compression is used on the YCbCr colour space on
the second pipe to have correct colours, we need to read a pixel from the
end of first pipe to accurately display colours. Hardware was programmed
properly to account for this extra pixel but it was not calculated
properly in software causing a split screen on some monitors.

[HOW]
The fix adjusts the second pipe's viewport and timings if the pixel
encoding is YCbCr422 or YCbCr420.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: George Shen &lt;george.shen@amd.com&gt;
Signed-off-by: Peterson Guo &lt;peterson.guo@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Enable Request rate limiter during C-State on dcn401</title>
<updated>2024-11-20T14:39:42+00:00</updated>
<author>
<name>Dillon Varone</name>
<email>dillon.varone@amd.com</email>
</author>
<published>2024-11-01T14:51:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=89713ce5518eda6b370c7a17edbcab4f97a39f68'/>
<id>89713ce5518eda6b370c7a17edbcab4f97a39f68</id>
<content type='text'>
[WHY]
When C-State entry is requested, the rate limiter will be disabled
which can result in high contention in the DCHUB return path.

[HOW]
Enable the rate limiter during C-state requests to prevent contention.

Cc: stable@vger.kernel.org # 6.11+
Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[WHY]
When C-State entry is requested, the rate limiter will be disabled
which can result in high contention in the DCHUB return path.

[HOW]
Enable the rate limiter during C-state requests to prevent contention.

Cc: stable@vger.kernel.org # 6.11+
Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Remove unused code</title>
<updated>2024-11-11T16:54:04+00:00</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>Rodrigo.Siqueira@amd.com</email>
</author>
<published>2024-11-05T15:50:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=28b24de43473f3e73341fcf0f3e21c562708f466'/>
<id>28b24de43473f3e73341fcf0f3e21c562708f466</id>
<content type='text'>
This commit removes a legacy debug_defaults_diags struct.

Reviewed-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This commit removes a legacy debug_defaults_diags struct.

Reviewed-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: disabling p-state checks for DCN31 and DCN314</title>
<updated>2024-11-08T16:45:30+00:00</updated>
<author>
<name>Emily Nie</name>
<email>Emily.Nie@amd.com</email>
</author>
<published>2024-10-16T19:52:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=0d5fd22b63bc8315ff946e7063be3bb031f7dda3'/>
<id>0d5fd22b63bc8315ff946e7063be3bb031f7dda3</id>
<content type='text'>
[Why]
IGT displays Dmesg warnings which are likely false

[How]
Disabling p-state checks leading to this warning for DCN31 and DCN314

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Emily Nie &lt;Emily.Nie@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[Why]
IGT displays Dmesg warnings which are likely false

[How]
Disabling p-state checks leading to this warning for DCN31 and DCN314

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Emily Nie &lt;Emily.Nie@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Remove last parts of timing_trace</title>
<updated>2024-11-04T16:26:36+00:00</updated>
<author>
<name>Dr. David Alan Gilbert</name>
<email>linux@treblig.org</email>
</author>
<published>2024-10-10T20:51:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=5fd95dab6094ba0b851767fc460c2806eaafe8bd'/>
<id>5fd95dab6094ba0b851767fc460c2806eaafe8bd</id>
<content type='text'>
Commit c2c2ce1e9623 ("drm/amd/display: Optimize passive update planes.")
removed the last caller of context_timing_trace.
Remove it.

With that gone, no one is now looking at the 'timing_trace' flag, remove
it and all the places that set it.

Signed-off-by: Dr. David Alan Gilbert &lt;linux@treblig.org&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Commit c2c2ce1e9623 ("drm/amd/display: Optimize passive update planes.")
removed the last caller of context_timing_trace.
Remove it.

With that gone, no one is now looking at the 'timing_trace' flag, remove
it and all the places that set it.

Signed-off-by: Dr. David Alan Gilbert &lt;linux@treblig.org&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Add P-State Stall Timeout Recovery Support for dcn401</title>
<updated>2024-10-28T20:32:35+00:00</updated>
<author>
<name>Dillon Varone</name>
<email>dillon.varone@amd.com</email>
</author>
<published>2024-10-11T17:51:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=c6df6213a95fa9674cc48d77042141942dd0809b'/>
<id>c6df6213a95fa9674cc48d77042141942dd0809b</id>
<content type='text'>
[WHY&amp;HOW]
Adds support for P-State stall timeout detection in DCHUBBUB.

Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[WHY&amp;HOW]
Adds support for P-State stall timeout detection in DCHUBBUB.

Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: Reuse subvp enable check for DCN401</title>
<updated>2024-10-22T21:50:38+00:00</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2024-10-07T19:50:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=41094c608a1115b2dd3571ae76461e59253e2ec2'/>
<id>41094c608a1115b2dd3571ae76461e59253e2ec2</id>
<content type='text'>
Reuse subvp enable check from DCN32 for IGT testing of Sub-Viewport
feature on DCN401

Reviewed-by: Rodrigo Siqueira &lt;rodrigo.siqueira@amd.com&gt;
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Reuse subvp enable check from DCN32 for IGT testing of Sub-Viewport
feature on DCN401

Reviewed-by: Rodrigo Siqueira &lt;rodrigo.siqueira@amd.com&gt;
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
