linux.git/drivers/gpu/drm/amd/display/dc/optc, branch v6.15 Linux kernel source tree drm/amd/display: Refactor DCN4x and related code 2025-02-25T16:44:02+00:00 Patel, Swapnil Swapnil.Patel@amd.com 2025-02-09T16:42:23+00:00 02a2793ab27e3aa3f345f4e7761005e5c9e3ebd4 [why & how] Refactor existing code related to DCN4x for better code sharing with other modules. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Swapnil Patel <Swapnil.Patel@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[why & how]
Refactor existing code related to DCN4x for better code sharing with
other modules.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Swapnil Patel <Swapnil.Patel@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Allow reuse of of DCN4x code 2025-02-13T02:03:01+00:00 Dmytro dmytro.laktyushkin@amd.com 2024-10-25T14:31:18+00:00 2739bd123782f9bedc39285b3965ff2b4b3e6411 Remove the static qualifier to make it available for code sharing with other components. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Dmytro <dmytro.laktyushkin@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Remove the static qualifier to make it available for code sharing
with other components.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Dmytro <dmytro.laktyushkin@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: log destination of vertical interrupt 2025-02-13T02:02:57+00:00 Josip Pavic Josip.Pavic@amd.com 2025-01-07T16:00:11+00:00 06b0a4ad7162b9dd7e52dbec320ea9d080d9e551 [Why] Knowing the destination of OTG's vertical interrupt 2 is useful for debugging, but it is not currently included in the OTG state readback logic [How] Read the OTG interrupt destination register to get the vertical interrupt 2 destination on ASICs that have this register when reading back the OTG state from hardware Reviewed-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[Why]
Knowing the destination of OTG's vertical interrupt 2 is useful for
debugging, but it is not currently included in the OTG state readback
logic

[How]
Read the OTG interrupt destination register to get the vertical interrupt
2 destination on ASICs that have this register when reading back the OTG
state from hardware

Reviewed-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add support to configure CRC window on specific CRC instance 2025-01-10T17:03:45+00:00 Wayne Lin Wayne.Lin@amd.com 2024-12-06T05:51:46+00:00 b6fcc3867d746c181d253b110236985b9b2ee2aa [Why] Have the need to specify the CRC window on specific CRC engine. dc_stream_configure_crc() today calculates CRC on crc engine 0 only and always resets CRC engine at first. [How] Add index parameter to dc_stream_configure_crc() for selecting the desired crc engine. Additionally, add another parameter to specify whether to skip the default reset of crc engine. Reviewed-by: HaoPing Liu <haoping.liu@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[Why]
Have the need to specify the CRC window on specific CRC engine.
dc_stream_configure_crc() today calculates CRC on crc engine 0 only and always
resets CRC engine at first.

[How]
Add index parameter to dc_stream_configure_crc() for selecting the desired crc
engine. Additionally, add another parameter to specify whether to skip the
default reset of crc engine.

Reviewed-by: HaoPing Liu <haoping.liu@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: DML2.1 Post-Si Cleanup 2025-01-10T17:00:34+00:00 Rafal Ostrowski rostrows@amd.com 2024-12-17T14:50:10+00:00 63ab80d9ac0adae2066b140ec30481ba4648140d [Why] There are a few cleanup and refactoring tasks that need to be done with the DML2.1 wrapper and DC interface to remove dependencies on legacy structures and N-1 prototypes. [How] Implemented pipe_ctx->global_sync. Implemented new functions to use pipe_ctx->hubp_regs and pipe_ctx->global_sync: - hubp_setup2 - hubp_setup_interdependent2 - Several other new functions for DCN 4.01 to support newer structures Removed dml21_update_pipe_ctx_dchub_regs Removed dml21_extract_legacy_watermark_set Removed dml21_populate_pipe_ctx_dlg_param Removed outdated dcn references in DML2.1 wrapper. Reviewed-by: Austin Zheng <austin.zheng@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Rafal Ostrowski <rostrows@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[Why]
There are a few cleanup and refactoring tasks that need to be done
with the DML2.1 wrapper and DC interface to remove dependencies on
legacy structures and N-1 prototypes.

[How]
Implemented pipe_ctx->global_sync.
Implemented new functions to use pipe_ctx->hubp_regs and
pipe_ctx->global_sync:
- hubp_setup2
- hubp_setup_interdependent2
- Several other new functions for DCN 4.01 to support newer structures

Removed dml21_update_pipe_ctx_dchub_regs
Removed dml21_extract_legacy_watermark_set
Removed dml21_populate_pipe_ctx_dlg_param
Removed outdated dcn references in DML2.1 wrapper.

Reviewed-by: Austin Zheng <austin.zheng@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Rafal Ostrowski <rostrows@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Extend dc_stream_get_crc to support 2nd crc engine 2025-01-06T19:44:26+00:00 Wayne Lin Wayne.Lin@amd.com 2024-07-23T07:01:05+00:00 10008a962b2d46e9672a89359d5740fa5c8fc9d7 [Why & How] Since now we can set multiple crc windows for secure display, add a new input parameter for dc_stream_get_crc to indicate to fetch crc from which crc engine. Reviewed-by: HaoPing Liu <haoping.liu@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[Why & How]
Since now we can set multiple crc windows for secure display, add a new input
parameter for dc_stream_get_crc to indicate to fetch crc from which crc
engine.

Reviewed-by: HaoPing Liu <haoping.liu@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add support for FAMS2+ interface versions 2024-12-18T17:18:33+00:00 Dillon Varone dillon.varone@amd.com 2024-11-29T21:37:32+00:00 55eeaaec0d5716efef2229bb2b5f262ba934f9a5 Current driver interface does not allow for flexibility in coexistence of multiple interface versions, so add support for checking minor interface revisions and providing appropriate programming. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Current driver interface does not allow for flexibility in coexistence
of multiple interface versions, so add support for checking minor
interface revisions and providing appropriate programming.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add 3DLUT FL HW bug workaround 2024-10-15T15:23:12+00:00 Ilya Bakoulin Ilya.Bakoulin@amd.com 2024-09-16T18:38:19+00:00 df60dcf5b58a642e531609d0d673bb63a11ed06e [Why] There is a known HW bug that causes the internal 3DLUT fetch signal to be lost at VREADY, regardless of whether the OTG lock is being held or not. A workaround is necessary to make sure that this internal signal stays up after OTG unlock. [How] Set the 3DLUT_ENABLE bit immediately before and after the unlock. Also use VUPDATE_KEEPOUT to prevent lock transition in the region between VSTARTUP and VREADY, which could cause issues with this WA sequence. Also including misc. 3DLUT DMA-related sequence fixes to address a few regressions causing corruption. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[Why]
There is a known HW bug that causes the internal 3DLUT fetch signal to
be lost at VREADY, regardless of whether the OTG lock is being held or
not. A workaround is necessary to make sure that this internal signal
stays up after OTG unlock.

[How]
Set the 3DLUT_ENABLE bit immediately before and after the unlock. Also
use VUPDATE_KEEPOUT to prevent lock transition in the region between
VSTARTUP and VREADY, which could cause issues with this WA sequence.

Also including misc. 3DLUT DMA-related sequence fixes to address a few
regressions causing corruption.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Wait for all pending cleared before full update 2024-10-01T21:30:47+00:00 Alvin Lee Alvin.Lee2@amd.com 2024-09-09T20:24:05+00:00 faee3edfcff750fe5dd760177f52978aefefeb70 [Description] Before every full update we must wait for all pending updates to be cleared - this is particularly important for minimal transitions because if we don't wait for pending cleared, it will be as if there was no minimal transition at all. In OTG we must read 3 different status registers for pending cleared, one specifically for OTG updates, one specifically for OPTC updates, and the last for surface related updates. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[Description]
Before every full update we must wait for all pending updates to be
cleared - this is particularly important for minimal transitions
because if we don't wait for pending cleared, it will be as if
there was no minimal transition at all. In OTG we must read 3 different
status registers for pending cleared, one specifically for OTG updates,
one specifically for OPTC updates, and the last for surface related
updates.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: restore immediate_disable_crtc for w/a 2024-07-27T21:32:15+00:00 Charlene Liu Charlene.Liu@amd.com 2024-07-16T17:47:43+00:00 9724b8494d3e85cb01c377f201bfaf25fd7d38ff [why] immediate_disable_crtc does not reset ODM. if switching to disable_crtc which will disable ODM as well. i.e. need to restore ODM mem cfg at reenable it at end of w/a. Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Xi (Alex) Liu <xi.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
[why]
immediate_disable_crtc does not reset ODM.  if switching to disable_crtc
which will disable ODM as well.  i.e. need to restore ODM mem cfg at
reenable it at end of w/a.

Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Xi (Alex) Liu <xi.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>